| Lids for wafer-scale optoelectronic packages -> Monitor Keywords |
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Lids for wafer-scale optoelectronic packagesRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Device Or Circuit Emissive Of Nonelectrical SignalLids for wafer-scale optoelectronic packages description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060121635, Lids for wafer-scale optoelectronic packages. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a Division of U.S. patent application Ser. No. 10/877,615, filed on Jun. 24, 2004, and incorporated herein by reference. FIELD OF INVENTION [0002] This invention relates to a method for creating a wafer of lids for wafer-scale optoelectronic packages. DESCRIPTION OF RELATED ART [0003] Optoelectronic (OE) devices are generally packaged as individual die. This means of assembly is often slow and labor intensive, resulting in higher product cost. Thus, what is needed is a method to improve the packaging of OE devices. SUMMARY [0004] In one embodiment of the invention, a method for forming a lid for a wafer-scale package includes (1) forming a cavity in a substrate, (2) forming an oxide layer over the cavity and over a bond area around the cavity on the substrate, (3) forming a reflective layer over the oxide layer, (4) forming a barrier layer over the reflective layer, (5) etching a portion of the barrier layer down to a portion of the reflective layer over the bond area, and (6) forming a solder layer on the portion of the reflective layer. In one embodiment, the reflective layer is a titanium-platinum-gold metal stack and the barrier layer is a titanium dioxide layer. BRIEF DESCRIPTION OF THE DRAWINGS [0005] FIGS. 1 and 2 are cross-sections of a wafer-scale optoelectronic package in one embodiment of the invention. [0006] FIG. 3 is a top view of a sub-mount of the optoelectronic package of FIGS. 1 and 2 in one embodiment of the invention. [0007] FIG. 4 is a flowchart of a method for making a lid for the wafer-scale optoelectronic package of FIGS. 1, 2, and 3 in one embodiment of the invention. [0008] FIGS. 5, 6, 7, 8, 9A, 9B, 10, 11, 12, 13, 14, 15, and 16 are the structures formed by the method of FIG. 4 in one embodiment of the invention. [0009] FIG. 17 is a mask used in the method of FIG. 1 in one embodiment of the invention. [0010] FIG. 18 is a flowchart of a method for making a lid for the wafer-scale optoelectronic package of FIGS. 1, 2, and 3 in another embodiment of the invention. [0011] FIGS. 19 and 20 are the structures formed by the method of FIG. 18 in one embodiment of the invention. [0012] Use of the same reference symbols in different figures indicates similar or identical items. The cross-sectional figures are not drawn to scale and are only for illustrative purposes. DETAILED DESCRIPTION [0013] FIGS. 1, 2, and 3 illustrate a wafer-scale optoelectronic package 150 including a sub-mount 80 and a lid 130 in one embodiment of the invention. Sub-mount 80 includes an optical lens 52 formed atop a substrate 54 and covered by an oxide layer 56. Buried traces 90, 92, 98, and 100 are formed atop oxide layer 56 and covered by a dielectric layer 64. Contact pads 82, 84, 86, and 88 (all shown in FIG. 3) are connected by plugs to buried traces 90, 92, 98, and 100, which are themselves connected by plugs to contact pads 94, 96, 102 and 104 (shown in FIG. 3) located outside of a seal ring 106. A laser die 122 is bonded atop contact pad 82 and wire bonded to contact pad 84, and a monitor photodiode die 124 is bonded atop contact pad 86 and wire bonded to contact pad 88. Seal ring 106 is connected to contact pads 108 and 110 for grounding purposes. [0014] Lid 130 includes a body 133 that defines a lid cavity 131 having a surface 132 covered by a reflective material 134. Lid cavity 131 provides the necessary space to accommodate the dies that are mounted on sub-mount 80. Reflective material 134 on surface 132 forms a 45 degree mirror 135 that reflect a light from laser die 122 to lens 52. A seal ring 136 is formed on the bond area along the edge of lid 130 around lid cavity 131. Reflective material 134 over lid cavity 131 also serves as an EMI shield when it is grounded through seal ring 136 and contact pads 108 and 110. In one embodiment, a barrier 322 is formed over reflective material 134 to define where seal ring 136 is to be formed. Barrier 322 confines seal ring 136 so the seal ring material (e.g., a solder) does not wick into cavity 131 and interfering with mirror 135. [0015] In one embodiment, lid 130 has a (100) crystallographic plane oriented at a 9.74 degree offset from a major surface 138. Lid 130 is anisotropically etched so that surface 132 forms along a (111) crystallographic plane. As the (100) plane of lid 130 is oriented at a 9.74 degree offset from major surface 138, the (111) plane and mirror 135 are oriented at a 45 degree offset from major surface 138. [0016] In one embodiment, an alignment post 140 is bonded to the backside of sub-mount 80. Alignment post 140 allows package 150 to be aligned with an optical fiber in a ferrule. [0017] FIG. 4 illustrates a method 200 for forming a wafer-scale lid 130 in one embodiment of the invention. [0018] In step 202, as shown in FIG. 5, nitride layers 302 and 304 are formed on the top and the bottom surfaces of a substrate 306, respectively. In one embodiment, substrate 306 is silicon having a thickness of about 675 microns, and nitride layers 302 and 304 are silicon nitride (SiN.sub.4) formed by low pressure chemical vapor deposition (LPCVD) and have a thickness of about 1000 to 2000 angstroms. In one embodiment, if adhesion of nitride layers 302 and 304 to a silicon substrate 306 becomes problematic, nitride layers 302 and 304 can be made low stress by modifying the gas ratio (dichlorosilante to ammonia) and the amount of gas flow. In one embodiment, if denser nitride layers 302 and 304 are needed to withstand a KOH etch, nitride layers 302 and 304 can be made silicon rich in order to become denser. Continue reading about Lids for wafer-scale optoelectronic packages... Full patent description for Lids for wafer-scale optoelectronic packages Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Lids for wafer-scale optoelectronic packages patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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