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Level-converting flip-flop and pulse generator for clustered voltage scalingLevel-converting flip-flop and pulse generator for clustered voltage scaling description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070188211, Level-converting flip-flop and pulse generator for clustered voltage scaling. Brief Patent Description - Full Patent Description - Patent Application Claims
PRIORITY STATEMENT [0001]This application claims priority under 35 USC .sctn. 119 to Korean Patent Application No. 2006-0014740, filed on Feb. 15, 2006, in the Korean Intellectual Property Office (KIPO), the entire contents of which are herein incorporated by reference. BACKGROUND [0002]1. Field [0003]Example embodiments relate to a level-converting flip-flop and a pulse generator for clustered voltage scaling. [0004]2. Description of the Related Art [0005]Mobile systems that may operate for a longer period of time with limited battery capacity have been increasingly developed over time. Thus, the need for semiconductor devices that operate at a lower voltage for use in mobile systems has increased. [0006]As such, various techniques have been introduced to reduce power consumption of semiconductor devices. One such technique is clustered voltage scaling. In clustered voltage scaling, a higher voltage may be applied to a critical path to increase the speed and a lower voltage may be applied to a non-critical path to reduce power consumption. [0007]In clustered voltage scaling, level converters may be needed between a region in which a higher voltage is applied and a region in which a lower voltage is applied as an interface between the regions. However, the more level converters used, the greater the power consumption may be. In order to reduce the number of level converters needed, a level converter may be located in an output terminal of each flip-flop (which may be most frequently used in a semiconductor integrated circuit). Also, in order to reduce or minimize power consumption caused by clock signals, it may be necessary for all flip-flops to operate at a lower supply voltage. As such, the operating speeds of the flip-flops may be reduced. [0008]If the flip-flops operate at a higher supply voltage, a higher number of level converters may be needed between a clock path and the flip-flops to reduce or prevent a reduction in the operating speed. This may cause overhead due to an increase in the area and power consumption of the system. Also, level converters may be needed in output terminals of the flip-flops, which may increase the area and power consumption of the system. SUMMARY [0009]Example embodiments provide a flip-flop having both the function of a level converter located in an output terminal of the flip-flop and the function of a level converter located in a clock input terminal, thereby increasing the operating speed of the flip-flop without increasing the area and power consumption of the flip-flop. Example embodiments also provide a level converting pulse generator for use in the flip-flop. [0010]According to example embodiments, there is provided a flip-flop comprising a pulse generator receiving an input clock signal with a high level equal to a first level and generating a pulse signal with a high level that may be converted into a second level higher than the first level, and a latch latching input data with a high level equal to a third level lower than the second level and outputting output data with a high level that may be converted into the second level in response to the pulse signal. [0011]The pulse generator may further receive an enable signal with a high level equal to a fourth level lower than the second level. The pulse generator may be enabled in response to the enable signal. [0012]The third and fourth levels may be equal to the first level. A supply voltage having the second level may be used as a supply voltage to the latch. [0013]According to example embodiments, a pulse generator may include an inversion delayer receiving an input clock signal with a high level equal to a first level and outputting a delayed, inverted input clock signal, a NAND gate performing a NAND operation on the input clock signal and the delayed, inverted input signal and outputting the result, and an inverter inverting a signal received from the NAND gate and outputting a pulse signal. [0014]A first supply voltage having the first level may be used as a supply voltage to the inversion delayer. A second supply voltage having a second level higher than the first level may be used as a supply voltage to the NAND gate and the inverter. Also, pulse generation and level conversion may be performed simultaneously. [0015]The NAND gate may further receive an enable signal with a high level equal to a third level lower than the second level. The third level may be equal to the first level. [0016]According to example embodiments, a pulse generator may comprise a NAND gate performing a NAND operation on a feedback signal and an input clock signal with a high level equal to a first level and outputting the operation result, and an inverter inverting a signal received from the NAND gate and outputting a pulse signal. The pulse generator may further comprise a PMOS transistor and an NMOS transistor being connected in series between a first supply voltage having the first level and a ground voltage, in which the input clock signal and the pulse signal may be supplied to gates of the PMOS transistor and the NMOS transistor, respectively, and a zero keeper storing the feedback signal which may be output at a point that connects the PMOS transistor and the NMOS transistor and may be at a logic low level. [0017]A second supply voltage having a second level higher than the first level may be used as a supply voltage to the NAND gate and the inverter. Also, pulse generation and level conversion may be simultaneously performed. [0018]The NAND gate may further include an enable signal with a high level equal to a third level lower than the second level. The third level may be equal to the first level. BRIEF DESCRIPTION OF THE DRAWINGS [0019]Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. FIGS. 1-6 represent non-limiting, example embodiments as described herein. [0020]FIG. 1 is a block diagram of a flip-flop according to example embodiments; Continue reading about Level-converting flip-flop and pulse generator for clustered voltage scaling... Full patent description for Level-converting flip-flop and pulse generator for clustered voltage scaling Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Level-converting flip-flop and pulse generator for clustered voltage scaling patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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