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Leffert Jay & Polglaze, P.A. patentsThe following is a sampling of recent Leffert Jay & Polglaze, P.A. patent applications (USPTO Patent Application #, Patent Title) sorted by month.
April 2008 - Leffert Jay & Polglaze, P.A. patents
20080094912 - Selective slow programming convergence in a flash memory device
20080089161 - Method for testing flash memory power loss recovery
20080090730 - Composition and method for killing nematodes and weeds in soils
March 2008 - Leffert Jay & Polglaze, P.A. patents
20080074933 - Random cache read
20080053387 - Valve mechanism lift adjustment device and method
20080055455 - Imbalance determination and correction in image sensing
February 2008 - Leffert Jay & Polglaze, P.A. patents
20080042126 - Ballistic direct injection nrom cell on strained silicon structures
January 2008 - Leffert Jay & Polglaze, P.A. patents
20080022351 - Streaming method and apparatus
20080014710 - Isolation regions
20080015693 - Spinal arthroplasty system
20080008006 - Programming method for nand eeprom
20080009117 - Band-engineered multi-gated non-volatile memory device with enhanced attributes
20080009946 - Distractible intervertebral implant
December 2007 - Leffert Jay & Polglaze, P.A. patents
20070285981 - Defective block handling in a flash memory device
20070285988 - Bitline exclusion in verification operation
20070279989 - Programming a non-volatile memory device
November 2007 - Leffert Jay & Polglaze, P.A. patents
20070272263 - Method for thickening hair, separator device for receiving hair, assembly for thickening hair and applicator for the assembly in the method for thickening hair
20070274150 - Non-volatile memory control
20070263462 - Nand architecture memory devices and operation
20070260493 - Attachment integrated claims systems and operating methods therefor
October 2007 - Leffert Jay & Polglaze, P.A. patents
20070242515 - Multiple select gate architecture with select gates of different lengths
20070242551 - User selectable banks for dram
20070227551 - Sticker for the application of hair and the like and related method of manufacturing
20070227687 - Die-casting system
20070230256 - Method and apparatus for filtering output data
20070230257 - Method and apparatus for filtering output data
September 2007 - Leffert Jay & Polglaze, P.A. patents
20070222555 - Security for anonymous vehicular broadcast messages
20070223702 - Digital certificate pool
20070210236 - Integrated mobile resource system
20070211536 - Programming a flash memory device
August 2007 - Leffert Jay & Polglaze, P.A. patents
20070203813 - Systems for receiving and forming marketplaces for working on digital information blocks
20070203837 - Exchange and integration of mixed data formats
20070203914 - Attachment integrated claims systems and operating methods therefor
20070195571 - Bit line coupling
20070195600 - Multiple level cell memory device with single bit per cell, re-mappable memory block
20070198596 - Attachment integrated claims systems and operating methods therefor
20070189099 - Power efficient memory and cards
July 2007 - Leffert Jay & Polglaze, P.A. patents
20070165459 - Flash memory array using adjacent bit line as source
20070166927 - Nrom flash memory devices on ultrathin silicon
20070168794 - Memory with element redundancy
20070168840 - Memory block quality identification in a memory device
20070162824 - Error detection and correction scheme for a memory device
June 2007 - Leffert Jay & Polglaze, P.A. patents
20070140012 - Nand architecture memory devices and operation
20070140004 - Sensing scheme for low-voltage flash memory
20070133294 - Flash memory programming to reduce program disturb
20070133312 - Flash with consistent latency for read operations
May 2007 - Leffert Jay & Polglaze, P.A. patents
20070114350 - Table accessory for supporting bags and the like
20070114633 - Integrated circuit device with a circuit element formed on an active region having rounded corners
20070115742 - Sense amplifier for a non-volatile memory device
20070117299 - Memory cells having underlying source-line connections
20070109871 - Nrom flash memory with self-aligned structural charge separation
20070096193 - Non-volatile memory device with tensile strained silicon layer
April 2007 - Leffert Jay & Polglaze, P.A. patents
20070084394 - Power generation in watercraft
20070084394 - Power generation in watercraft
February 2007 - Leffert Jay & Polglaze, P.A. patents
20070036002 - Programming flash memories
20070038800 - Contiguous block addressing scheme
20070038828 - Chip protection register lock circuit in a flash memory device
20070028466 - Linear distance measurement by non-driven arm
20070030739 - Method of comparison between cache and data register for non-volatile memory
20070031773 - Bracket for orthodontics
20070032035 - Container capacitor structure and method of formation thereof
20070033363 - Method for reading while writing to a single partition flash memory
20070028036 - Top/bottom symmetrical protection scheme for flash
January 2007 - Leffert Jay & Polglaze, P.A. patents
20070022332 - Background block erase check for flash memories
20070012978 - Junction-isolated depletion mode ferroelectric memory devices and systems
20070012988 - High density nand non-volatile memory device
20070006974 - Tape applicator
20070011449 - Attachment integrated claims systems and operating methods therefor
20070002271 - Glass frames
20070002630 - Low power multiple bit sense amplifier
December 2006 - Leffert Jay & Polglaze, P.A. patents
20060278913 - Non-volatile memory cells without diffusion junctions
20060282644 - Robust index storage for non-volatile memory
20060273576 - Hydraulic joint articulated device and use thereof with a heat radiator
November 2006 - Leffert Jay & Polglaze, P.A. patents
20060267070 - Gate coupling in floating-gate memory cells
20060267072 - Scalable high density non-volatile memory cells in a contactless memory array
20060267075 - Multi-state memory cell
20060268613 - User configurable commands for flash memory
20060268614 - User configurable commands for flash memory
20060270181 - Methods of forming integrated circuit devices
20060271725 - Version based non-volatile memory translation layer
20060260473 - Insulated platter
20060261853 - Output buffer strength trimming
20060262602 - Nand flash cell structure
20060262624 - Method and architecture to calibrate read operatons in synchronous flash memory
20060255400 - One-transistor composite-gate memory
20060256565 - Modular lighting device
20060256624 - Erase block data splitting
20060256633 - Handling defective memory blocks of nand memory devices
20060258093 - Nand memory arrays
20060258095 - High coupling memory cell
20060259647 - Logic and memory device integration
20060259714 - Memory device controller
20060259829 - Program failure recovery
20060252208 - Flash memory with metal-insulator-metal tunneling program and erase
20060253641 - Multiple erase block tagging in a flash memory device
20060244038 - Split gate flash memory cell with ballistic injection
20060245255 - High density stepped, non-planar flash memory
20060245256 - Split gate flash memory cell with ballistic injection
20060246664 - Memory with metal-insulator-metal tunneling program and erase
20060248268 - Defective memory block identification in a memory device
20060248368 - Fast data access mode in a memory device
October 2006 - Leffert Jay & Polglaze, P.A. patents
20060237775 - Memory device with high dielectric constant gate dielectrics and metal floating gates
20060239074 - Using redundant memory for extra features
20060239091 - Using redundant memory for extra features
20060239904 - Utilization of lead shavings in abrasion mills for the production of lead oxide
20060242484 - Memory block quality identification in a memory device
20060242485 - Error detection, documentation, and correction in a flash memory device
20060234393 - Scalable high density non-volatile memory cells in a contactless memory array
20060236207 - Error detection, documentation, and correction in a flash memory device
20060226471 - Flash memory cells with reduced distances between cell elements
20060227612 - Common wordline flash array architecture
20060230225 - Random access interface in a serial memory device
20060221670 - In-service reconfigurable dram and flash memory device
20060221736 - Data compression read mode for memory testing
20060221737 - Data compression read mode for memory testing
September 2006 - Leffert Jay & Polglaze, P.A. patents
20060208305 - In-service reconfigurable dram and flash memory device
20060208309 - Non-planar flash memory having shielding between floating gates
20060209596 - Multiple level programming in a non-volatile memory device
20060211201 - High coupling memory cell
20060203553 - Nand string wordline delay reduction
20060203595 - Multiple memory device management
20060205132 - Scalable integrated logic and non-volatile memory
20060197138 - Use of selective epitaxial silicon growth in formation of floating gates
20060197143 - Apparatus and method for split transistor memory having improved endurance
20060198070 - Methods, circuits, and applications using a resistor and a schottky diode
20060198194 - Noise suppression in memory device sensing
20060198212 - Decoder for memory data bus
20060198217 - Multiple level cell memory device with single bit per cell, re-mappable memory block
20060198221 - Minimizing adjacent wordline disturb in a memory device
20060198222 - Minimizing adjacent wordline disturb in a memory device
August 2006 - Leffert Jay & Polglaze, P.A. patents
20060192242 - Low power memory subsystem with progressive non-volatility
20060192243 - Embedded trap direct tunnel non-volatile memory
20060193177 - Position based erase verification levels in a flash memory device
20060193178 - Non-volatile memory device with erase address register
20060186530 - Memory device power distribution in memory assemblies
20060187573 - Sensor equipment guard
20060187716 - Reduction of adjacent floating gate data pattern sensitivity
20060180876 - High density stepped, non-planar nitride read only memory
20060181930 - Erase verify for non-volatile memory
20060176726 - Integrated dram-nvram multi-level memory
20060170050 - Fully depleted silicon-on-insulator cmos logic
20060171232 - High speed low voltage driver
20060172493 - Forming multi-layer memory arrays
July 2006 - Leffert Jay & Polglaze, P.A. patents
20060163644 - Scalable high density non-volatile memory cells in a contactless memory array
20060164034 - Hybrid vehicle equipped with a variable voltage battery
20060164907 - Multiple flash memory device management
20060166443 - Multi-state nrom device
20060158916 - Programable identification circuitry
20060152962 - Integrated dram-nvram multi-level memory
20060152963 - Integrated dram-nvram multi-level memory
20060152978 - Multi-state nrom device
20060156084 - Multiphase clock generation
20060156093 - Synchronous memory interface with test code input
20060146594 - Integrated dram-nvram multi-level memory
20060146605 - Integrated dram-nvram multi-level memory
20060146606 - Integrated dram-nvram multi-level memory
20060146611 - Flash memory device with improved programming performance
20060149897 - Flash memory programming
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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Leffert Jay & Polglaze, P.A. in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Leffert Jay & Polglaze, P.A. with additional patents listed. Browse our Agent directory for other possible listings.
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