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Browse: A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | 1 | 3 | Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patentsThe following is a sampling of recent Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patent applications (USPTO Patent Application #, Patent Title) sorted by month.January 2011 - Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patents 20110022932 - Variable sector-count ecc December 2010 - Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patents 20100306626 - Methods of data handling October 2010 - Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patents 20100264482 - Memory cells configured to allow for erasure by enhanced f-n tunneling of holes from a control gate to a charge trapping material 20100259992 - Methods and apparatus for programming a memory cell using one or more blocking memory cells September 2010 - Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patents 20100241798 - Robust index storage for non-volatile memory August 2010 - Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patents 20100202202 - Adjusting for charge loss in a memory April 2010 - Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patents 20100091565 - M+n bit programming and m+l bit read for m bit memory cells July 2009 - Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patents 20090190404 - Nand flash content addressable memory 20090187689 - Non-volatile memory with lpdram 20090172342 - Robust index storage for non-volatile memory June 2009 - Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patents 20090154254 - Cluster based non-volatile memory translation layer May 2009 - Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patents 20090115479 - Methods and apparatus for synchronizing with a clock signal April 2009 - Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patents 20090103365 - Sensing of memory cells in nand flash 20090103365 - Sensing of memory cells in nand flash 20090103365 - Sensing of memory cells in nand flash 20090097318 - Programming sequence in nand memory January 2009 - Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patents 20090027963 - High performance multi-level non-volatile memory device 20090019340 - Non-systematic coded error correction October 2008 - Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patents 20080253188 - Programming method to reduce gate coupling interference for non-volatile memory August 2008 - Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patents 20080205147 - Local self-boost inhibit scheme with shielded word line April 2008 - Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patents 20080082886 - Sub-instruction repeats for algorithmic pattern generators March 2008 - Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth patents 20080062762 - Nand architecture memory with voltage sensing ### This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth with additional patents listed. Browse our Agent directory for other possible listings. ### FreshPatents.com Support - Terms & Conditions |