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Lead frame with included passive devicesLead frame with included passive devices description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20080036034, Lead frame with included passive devices. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001]This application claims the benefit of U.S. Provisional Patent Application No. 60/449,049, filed Feb. 21, 2003, which is incorporated by reference herein in its entirety. BACKGROUND OF THE INVENTION [0002]1. Field of the Invention [0003]The present invention relates generally to semiconductor device packages and, more particularly, to lead frame based semiconductor device packages including at least one passive device. [0004]2. Description of the Related Art [0005]In a conventional semiconductor device package, a housing encases the semiconductor device (die) to prevent damage to the die from exposure to the environment. The housing may be hermetically sealed, encased in plastic, or otherwise protected from the environment. [0006]In lead frame based semiconductor device packages, electrical signals are transmitted between at least one die and external circuitry, such as a printed circuit board, by an electrically conductive lead frame. The lead frame includes a number of leads, each having an inner lead end and an opposing outer lead end. The inner lead end is electrically connected to input/output (I/O) pads on the die, and the outer lead end provides a terminal outside of the package body. Where the outer lead end terminates at the face of the package body, the package is known as a "no-lead" package, while if the outer leads extend beyond the package body perimeter the package is referred to as "leaded". Examples of well-known no-lead packages include quad flat no-lead (QFN) packages, which have four sets of leads disposed around the perimeter of the bottom of a square package body, and dual flat no-lead (DFN) packages, which have two sets of leads disposed along opposite sides of the bottom of a package body. A method for the manufacture of a lead frame based package is disclosed in commonly owned U.S. patent application Ser. No. 10/134,882 that was filed on Apr. 29, 2002 and is incorporated by reference in its entirety herein. [0007]In many electronic assemblies, passive components such as, for example, capacitors, inductors and resistors, are interconnected with semiconductor device packages to provide desired functions. Heretofore, most of these passive components could not be integrated within an encased die package in a cost effective manner. [0008]It is desirable from both a manufacturer's and user's standpoint that electronic assemblies require as few as possible external connections since such connections increase manufacturing costs (that are ultimately passed to the user) and can introduce noise to the package as signals are propagated from external components. [0009]Accordingly, the inventors have realized that a need exists for an improved semiconductor device package including a cost effective method for placing passive components close to a die and for encasing the passive components and die in a single package. BRIEF SUMMARY OF THE INVENTION [0010]The above-described and other drawbacks and deficiencies of the prior art are overcome or alleviated by a semiconductor device package, comprising: a package body; a semiconductor device disposed within the package body; at least one passive device disposed within the package body; and a lead frame formed from electrically conductive material. The lead frame includes a plurality of leads electrically connected to I/O pads on the semiconductor device, a first surface exposed from the package body, and a plurality of first interposers electrically connected to the at least one passive device. The at least one passive device may be selected from capacitors; inductors and resistors. The package body may be formed by a mold compound encapsulating at least a portion of the semiconductor die, at least a portion of the at least one passive component, and at least a portion of the lead frame. The leads may be exposed substantially coplanar with a surface of the package body. [0011]The I/O pads on the semiconductor device may be wire bonded or tape bonded to the plurality of leads. In one embodiment, the lead frame further includes a die pad, with the semiconductor device being secured to the die pad. In another embodiment, a portion of the semiconductor device is exposed from the package body. Alternatively, the I/O pads on the semiconductor device are soldered to bond sites on second interposers, which are attached to the plurality of leads for forming a flip-chip attachment. Support posts may be disposed beneath the bond sites on the first and/or second interposers, with the support posts being exposed at a surface of the package body. [0012]In another aspect, a semiconductor device package comprises: a molding compound forming at least a portion of a first package face; at least one passive device at least partially covered by the molding compound; a semiconductor device at least partially covered by the molding compound, the semiconductor device including a plurality of I/O pads; and a lead frame formed from electrically conductive material and partially covered by the molding compound. The lead frame includes: a plurality of leads, each having a first surface forming a bond site electrically connected to at least one I/O pad in the plurality of I/O pads and a second surface exposed at the first package face, and a plurality of interposers electrically connected to the at least one passive device. The plurality of interposers each has a third surface coplanar with the first surfaces of the plurality of leads, and at least a portion of each interposer in the plurality of interposers being spaced apart from the first package face. [0013]In yet another aspect, a method of forming a semiconductor device package comprises: forming a lead frame from an electrically conductive material, including: forming a plurality of leads and a plurality of first interposers in the conductive material, and etching a bottom surface of the plurality of leads and the plurality of interposers, the etching defining a plurality of first surfaces on the contacts; electrically connecting I/O pads on a semiconductor device to the plurality of leads; electrically connecting at least one passive device across pairs of first interposers in the plurality of interposers; and covering at least a portion of each of the lead frame, the semiconductor device, and the at least one passive device with a molding compound. The molding compound forms at least a portion of a first package face. The first surface of each lead is exposed at the first package face and at least a portion of each first interposer is spaced apart from the first package face. [0014]The I/O pads on the semiconductor device may be wire bonded or tape bonded to the plurality of leads. Forming the lead frame may further include forming a die pad from the electrically conductive material. In this embodiment, the method further comprises securing the semiconductor device to the die pad. In another embodiment, a portion of the semiconductor device is exposed at the first package face. In yet another embodiment, electrically connecting the 1/0 pads on the semiconductor device to the plurality of leads includes soldering the I/O pads to bond sites on the lead frame for forming a flip-chip attachment. In this embodiment, forming the lead frame may further include forming a plurality of second interposers connected to the plurality of leads, with the bond sites being formed on the second interposers. Also in this embodiment, the etching may further define support posts disposed beneath the bond sites on the second interposers, with the support posts being exposed at the first package face after the covering with the molding compound. [0015]In the method, the etching may further define a support post extending from at least one of the first interposers in the plurality of first interposers, with the support post being exposed at the first package face after the covering with the molding compound. The support post and the first surface of each lead may be adhered to a surface before covering with the molding compound. [0016]The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the invention will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS [0017]The invention will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings wherein like elements are numbered alike, and in which: [0018]FIG. 1 is a perspective, partial cross sectional view of a lead frame based semiconductor device package with included passive devices in accordance with one embodiment of the present invention; [0019]FIG. 2 is a top view of a lead frame for the device of FIG. 1; [0020]FIG. 3 is a bottom view of the lead frame of FIG. 2; Continue reading about Lead frame with included passive devices... Full patent description for Lead frame with included passive devices Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Lead frame with included passive devices patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Lead frame with included passive devices or other areas of interest. ### Previous Patent Application: One-time programmable memory Next Patent Application: Method for manufacturing a passive integrated matching network for power amplifiers Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the Lead frame with included passive devices patent info. IP-related news and info Results in 0.12347 seconds Other interesting Feshpatents.com categories: Electronics: Semiconductor , Audio , Illumination , Connectors , Crypto , 174 |
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