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Latest producer tracking in an out-of-order processor, and applications thereof

USPTO Application #: 20080016326
Title: Latest producer tracking in an out-of-order processor, and applications thereof
Abstract: A processor and system for latest producer tracking. In one embodiment, the processor includes an operand renamer circuit that includes a register rename map, a producer tracking circuit that includes a producer tracking map, and a results buffer allocater circuit that includes a results buffer free list. Control logic modifies in-register status values stored in the register rename map based on producer tracking status values stored in the producer tracking map. The producer tracking status values stored in the producer tracking map are modified based on buffer identification values output by the results buffer allocater circuit. (end of abstract)
Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c. - Washington, DC, US
Inventors: Kjeld Svendsen, Xing Yu Jiang
USPTO Applicaton #: 20080016326 - Class: 712217 (USPTO)

The Patent Description & Claims data below is from USPTO Patent Application 20080016326.
Brief Patent Description - Full Patent Description - Patent Application Claims  monitor keywords

CROSS REFERENCE TO RELATED APPLICATION

[0001]This application is related to commonly owned U.S. patent application Ser. No. ______, titled "Method For Latest Producer Tracking In An Out-Of-Order Processor, And Applications Thereof," filed on the same day herewith (Attorney Docket No. 1778.2370001), which is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

[0002]The present invention relates generally to processors and more particularly to processors having an out-of-order execution pipeline.

BACKGROUND OF THE INVENTION

[0003]Reduced Instruction Set Computer (RISC) processors are well known. RISC processors have instructions that facilitate the use of a technique known as pipelining. Pipelining enables a processor to work on different steps of an instruction at the same time and thereby take advantage of parallelism that exists among the steps needed to execute an instruction. As a result, a processor can execute more instructions in a shorter period of time. Additionally, modern Complex Instruction Set Computer (CISC) processors often translate their instructions into micro-operations (i.e., instructions similar to those of a RISC processor) prior to execution to facilitate pipelining.

[0004]Many pipelined processors, especially those used in the embedded market, are relatively simple in-order machines. As a result, they are subject to control, structural, and data hazard stalls. More complex processors have out-of-order execution pipelines. These more complex processors, often referred to as out-of-order processors, schedule execution of instructions around hazards that would stall an in-order machine.

[0005]Register renaming is a technique used by out-of-order processors to avoid unnecessary serialization of program operations imposed by the reuse of logical registers. In a conventional out-of-order processor, register renaming is implemented using a custom content-addressable memory (CAM) that holds a register map. The register map identifies associations formed between physical registers and logical registers. The CAM register map is searched, for example, during instruction decode and dispatch operations to identify physical registers that hold the latest results for source logical registers specified by an instruction.

[0006]In a conventional out-of-order processor, other register status information such as, for example, information that indicates whether register data is available in a register file or off a bypass is also maintained in a custom CAM. While custom CAMs and conventional out-of-order processing techniques work for their intended purposes, they are costly to implement in terms of chip area, power consumption, and processing speed. As a result, especially in the embedded market, the number of applications in which a conventional out-of-order processor may be used is restricted.

[0007]What are needed are new techniques for implementing out-of-order processing that overcome the limitations associated with conventional techniques.

BRIEF SUMMARY OF THE INVENTION

[0008]The present invention provides a processor and system for latest producer tracking, and applications thereof. In one embodiment, the processor includes an operand renamer circuit that includes a register rename map, a producer tracking circuit that includes a producer tracking map, and a results buffer allocater circuit that includes a results buffer free list.

[0009]The register rename map associates particular physical registers of a results buffer with particular logical/architectural state registers of a register file. The register rename map is indexed using register identification (RID) values. Each RID value represents a logical/architectural state register of the register file. The register rename map stores buffer identification (BID) values and in-register (INR) status values. Each BID value represents a physical register of a results buffer. The INR values are used to determine whether particular data values are available in a logical/architectural state register of the register file or in a physical register of the results buffer.

[0010]The producer tracking map stores producer tracking status values. These status values are used to identify which physical registers of the results buffer are being used by instructions to store the latest data prior to the data being transferred to logical/architectural state registers of the register file. The producer tracking status values stored in the producer tracking map are modified in one embodiment by placing BID values produced by the results buffer allocater circuit on a BID set bus or a BID clear bus of the producer tracking circuit.

[0011]The results buffer free list stores status values that identify which physical registers of the results buffer are available to store a value produced by an instruction. Instructions that produce values are assigned physical registers in which their results can be stored until instruction graduation. The function of the results buffer allocater circuit is to keep track of physical register availability and to output a BID value representing a physical register, which can be assigned to an instruction and used to store the value produced by the instruction.

[0012]Control logic modifies the INR status values stored in the register rename map based on the producer tracking status values stored in the producer tracking map.

[0013]Further embodiments, features, and advantages of the present invention, as well as the structure and operation of the various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

[0014]The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.

[0015]FIG. 1 is a diagram of a processor according to an embodiment of the present invention.

[0016]FIG. 2 is a more detailed diagram of the processor of FIG. 1.

[0017]FIG. 3 is a diagram illustrating a relationship between a producer tracking map, a register rename map, and a results buffer free list of a processor according to an embodiment of the present invention.

[0018]FIG. 4 is a diagram that illustrates clearing a status bit of a producer tracking map according to an embodiment of the present invention.

[0019]FIG. 5 is a diagram that illustrates setting a status bit of a producer tracking map and updating a register rename map according to an embodiment of the present invention.

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Early access to microcode rom
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Method and apparatus for register renaming using multiple physical register files and avoiding associative search
Industry Class:
Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)

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