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J. Mike Amerson, Williams Morgan & Amerson, P.C. patentsThe following is a sampling of recent J. Mike Amerson, Williams Morgan & Amerson, P.C. patent applications (USPTO Patent Application #, Patent Title) sorted by month.
April 2008 - J. Mike Amerson, Williams Morgan & Amerson, P.C. patents
20080081403 - Method for reducing crystal defects in transistors with re-grown shallow junctions by appropriately selecting crystalline orientations March 2008 - J. Mike Amerson, Williams Morgan & Amerson, P.C. patents
20080054415 - n-channel field effect transistor having a contact etch stop layer in combination with an interlayer dielectric sub-layer having the same type of intrinsic stress 20080059527 - System and method for standardized process monitoring in a complex manufacturing environment January 2008 - J. Mike Amerson, Williams Morgan & Amerson, P.C. patents
20080023692 - Transistor having a strained channel region including a performance enhancing material composition 20080026487 - Method of forming an etch indicator layer for reducing etch non-uniformities 20080026531 - Field effect transistor and method of forming a field effect transistor 20080026572 - Method for forming a strained transistor by stress memorization based on a stressed implantation mask 20080003825 - Method of patterning gate electrodes by reducing sidewall angles of a mask layer 20080003830 - Reducing contamination of semiconductor substrates during beol processing by providing a protection layer at the substrate edge December 2007 - J. Mike Amerson, Williams Morgan & Amerson, P.C. patents
20070278484 - Method and test structure for estimating electromigration effects caused by porous barrier materials 20070278596 - Method of increasing transistor drive current by recessing an isolation trench November 2007 - J. Mike Amerson, Williams Morgan & Amerson, P.C. patents
20070254461 - Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same October 2007 - J. Mike Amerson, Williams Morgan & Amerson, P.C. patents
20070228377 - Semiconductor device comprising soi transistors and bulk transistors and a method of forming the same August 2007 - J. Mike Amerson, Williams Morgan & Amerson, P.C. patents
20070178690 - Semiconductor device comprising a metallization layer stack with a porous low-k material having an enhanced integrity 20070179652 - Method and system for scheduling a stream of products in a manufacturing environment by using a simulation process July 2007 - J. Mike Amerson, Williams Morgan & Amerson, P.C. patents
20070166982 - Method of forming a metal layer over a patterned dielectric by wet chemical deposition including an electroless and a powered phase 20070152343 - Semiconductor device comprising a contact structure with increased etch selectivity May 2007 - J. Mike Amerson, Williams Morgan & Amerson, P.C. patents
20070123009 - Technique for increasing adhesion of metallization layers by providing dummy vias 20070123043 - A semiconductor device comprising a copper alloy as a barrier layer in a copper metallization layer 20070123044 - Method of forming an insulating capping layer for a copper metallization layer by using a silane reaction 20070096195 - Technique for providing multiple stress sources in nmos and pmos transistors 20070096148 - Embedded strain layer in thin soi transistors and a method of forming the same March 2007 - J. Mike Amerson, Williams Morgan & Amerson, P.C. patents
20070044544 - Method and apparatus for determining surface characteristics by using spm techniques with acoustic excitation and real-time digitizing February 2007 - J. Mike Amerson, Williams Morgan & Amerson, P.C. patents
20070023918 - Technique for forming a copper-based contact layer without a terminal metal
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