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  Inventory tracking mechanism for virtual wafer circuit probing subcontractUSPTO Application #: 20060010039Title: Inventory tracking mechanism for virtual wafer circuit probing subcontract Abstract: The present disclosure provides an inventory tracking method for use with semiconductor product. The method can be used to track wafer lots transferred from a front end such as a fabrication (fab) facility, to a back end such as a wafer circuit probe facility. The method includes tracking a lot of wafers being sent to the back end facility and receiving a status report from the back end facility. The status report is compared to a predetermined criteria, and the lot is designated as a first type, such as slow moving, if the status report fails to meet the predetermined criteria. A payment plan is then associated with the lot due to it being designated as slow moving. (end of abstract)
Agent: Haynes And Boone, LLP - Dallas, TX, US Inventors: Chia-Ho Yang, Ming Ta Hsu, Shau Tsung Yu, Su Mei Chang, Tien-Hui Chang USPTO Applicaton #: 20060010039 - Class: 705022000 (USPTO) Related Patent Categories: Data Processing: Financial, Business Practice, Management, Or Cost/price Determination, Automated Electrical Financial Or Business Practice Or Management Arrangement, Including Point Of Sale Terminal Or Electronic Cash Register, Inventory Monitoring The Patent Description & Claims data below is from USPTO Patent Application 20060010039. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF DISCLOSURE [0001] The present disclosure relates generally to semiconductor manufacturing entities such as wafer fabrication facilities and circuit probing facilities, more particularly, to a method and system for facilitating invoicing and payment between entities in a semiconductor manufacturing environment. BACKGROUND [0002] The semiconductor business has gone through many recent changes. One of the changes is that a chip provider may not be the same entity that manufactures the chip. For example, a first entity can come up with a chip design, a second entity can produce a mask set for the design, a third entity can fabricate wafers on which the chips (referred to as die) are located, a fourth entity can test the die on the wafer (referred to as circuit probe), a fifth entity can perform assembly, a sixth entity can perform final test, and a seventh entity can market and/or sell the final chips. Any of these entities can be a customer to the other, and a single entity (e.g., the one who markets and/or sells the final chips) may be a customer to all of the entities. [0003] It is important to properly allocate costs among all the entities involved in manufacturing the chips. For example, when a front end such as wafer fabrication facility (fab) ships product to a back end such as a wafer circuit probe facility, there is an opportunity to bill the customer at that time. In a quote-by-wafer (QBW) scenario, the fab will invoice the customer when the wafers are shipped to the wafer circuit probe. In this scenario, the customer purchases wafers, independent of circuit probe yield. If there are defective wafers (e.g., a wafer fails to meet a predetermined yield), the fab can then refund the customer some or all of the payment. For example, the refund may be prorated according to the wafer yield. In a quote-by-die (QBD) scenario, the fab ships the wafers to wafer circuit probe, but holds off on billing the customer. The probe yield is then reported to the fab, and the fab invoices the customer for the good die. [0004] There are many problems associated with the above-described scenarios. For example, handling refunds is difficult and cost-ineffective. Also, in QBD scenarios, billing is often delayed for longer-than-expected time periods. Accordingly, what is needed is a system and method that addresses one or more of these problems. Additionally and/or alternatively, what is needed is a system and method that can be used in such a manufacturing environment. BRIEF DESCRIPTION OF THE DRAWINGS [0005] FIG. 1 is a block diagram of a front end, a back end, and a customer in a business environment that can benefit from one or more embodiments of the present invention. [0006] FIG. 2 is an expanded schematic view of the environment of FIG. 1, with additional details and examples of different embodiments. [0007] FIG. 3 is a flow chart of a method for implementing an inventory tracking routine according to one or more embodiments of the present invention. [0008] FIGS. 4 and 5 are message flow diagrams for implementing an inventory tracking routine according to one or more embodiments of the present invention. DETAILED DESCRIPTION [0009] It is to be understood that the following disclosure provides many different examples for implementing different embodiments of the present invention. Also, specific examples of components and arrangements of components are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the relationship of a first entity with a second entity in the description that follows may include embodiments in which the first and second entities are in direct communication, and may also include embodiments in which additional entities may be interposed between the first and second entities, such that the first and second entity may not be in direct communication. [0010] Referring to FIG. 1, a semiconductor business system 100 can benefit from one or more embodiments of the present invention. According to one embodiment, the system 100 includes a customer 102, a front end 104, and a back end 106. In the present embodiment, the front and back end indicate facilities used in the manufacture of semiconductor integrated circuits. As a further example, the front end 104 is a first process, such as a fabrication facility (fab), and the back end 106 is a second process, such as a wafer circuit probe facility. In continuance of the example, the customer 102 has employed the front end 104 to fabricate one or more semiconductor wafers, and has employed the back end to test the wafers. [0011] It is understood that there are other examples that can also benefit from the present invention. The front end 104 can be a circuit design house and the back end 106 can be a fab that also performs wafer circuit probe. In yet another example, the front end 104 can be a circuit probe facility and the back end 106 can be an assembly facility and/or a final test facility. Additional examples also exist outside of the semiconductor manufacturing environment. [0012] Referring now to FIG. 2, in continuation of the first example discussed above, the front end 102 includes a plurality of entities. The entities include one or more internal entities such as a service system 202, the actual fab equipment 204, and/or an engineering system 206, and may also include an external entity such as a design facility or lab 208. One or more of the entities 202-208 may be interconnected by a communications network 210. The network 210 may be a single network or may be a variety of different networks, such as an intranet and the Internet, and may include both wireline and wireless communication channels. The connections can use digital communications such as internet protocol, analog communications such as traditional telephone dial-up communications, or combinations thereof. [0013] Each of the entities 202-208 may include one or more computing devices such as personal computers, personal digital assistants, pagers, cellular telephones, and the like. For the sake of example, the service system 202 is expanded to show a central processing unit (CPU) 222, a memory unit 224, an input/output (I/O) device 226, and an external interface 228. The external interface may be, for example, a modem, a wireless transceiver, and/or one or more network interface cards (NICs). The external interface may also include a browser software so that one interface can be made to the customer 102 and a separate interface can be made to the back end 106, using essentially the same hardware but different software instances. [0014] The components 222-228 are interconnected by a bus system 230. It is understood that the service system 202 may be differently configured and that each of the listed components may actually represent several different components. For example, the CPU 222 may actually represent a multi-processor or a distributed processing system; the memory unit 224 may include different levels of cache memory, main memory, hard disks, and remote storage locations; and the I/O device 226 may include monitors, keyboards, and the like. [0015] The fab facility 204 includes one or more computing devices 240, 242. These computing devices can be attached to equipment that performs processing operations, or may be adjunct systems used by the fab in general. The engineering entity 206 includes one or more computing devices 244. The design/lab facility 208 also includes one or more computing devices 246, 248. [0016] It is also understood that the customer 102 may include one or more computing devices 250 and the back end 106 may include one or more computing devices 252. It is further anticipated that the communications internal to the front end 104 may be of one type, and the communications between the front end and the customer 102 and/or the back end 106 may be of another type, and may utilize different networks altogether. [0017] Referring now to FIG. 3, the service system 202 (FIG. 2) can perform a method 300 for inventory tracking and billing the customer 102 for wafers processed by the front end 104 and back end 106. It is understood that the method 300 can also or alternatively be performed by either the customer 102 or the backend 106, and/or may have functionality distributed therebetween. In the present embodiment, the method 300 provides a modification to the quote-by-die (QBD) method of billing that provides some of the benefits normally associated with the quote-by-wafer (QBW) method of billing. [0018] Execution begins at step 302 where a shipment is made to the back end 106. In the present example, the shipment will include one or more "lots," each lot including one or more wafers. In the present embodiment, the lots do not require further processing at the front end 104, although other embodiments may require that the lots be sent back to the front end after being processed at the back end 106. [0019] At step 304, a "Receive Receipt" is received at the front end 104 indicating that the back end 106 has received the product in question. The Receive Receipt can be automatically delivered, for example, through the network 210 (FIG. 2) in a computer-to-computer communication between the back end 106 and the service system 202 of the front end 104. [0020] At step 306, a determination is made as to whether each of the received lots is in a "normal" backend flow. A normal backend flow is one that produces expected results or information within an expected time frame. For example, it may be expected that the back end produce yield status reports within 4 weeks of receiving a wafer lot. Also, there may be several reports, such as an initial yield status report and a second report after additional testing. Initially, it can be assumed that a normal backend flow exists, although this may not always be the case. Continue reading... Full patent description for Inventory tracking mechanism for virtual wafer circuit probing subcontract Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Inventory tracking mechanism for virtual wafer circuit probing subcontract patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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