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Interposer for connecting plurality of chips and method for manufacturing the same

Interposer for connecting plurality of chips and method for manufacturing the same description/claims

1. Field of the Invention

The invention is related to an interposer, and particularly to an interposer capable of connecting several chips and reducing the size of a package having the interposer therein.

2. Description of the Prior Art

In recent years, consumer electronic devices have become smaller and lighter. In addition, high performance, high speed, large capacity, multi-functionality, and less electrical consumption are desired goals promoting technical development of these electric products.

Please refer to FIG. 1, which is a schematic diagram of a conventional package 10. FIG. 1 shows a package 10 having a package substrate 12 and two chips 14, 16 respectively disposed on each surface thereof. The chips 14, 16 have a plurality of respective contact pads 14A, 14B, 16A, 16B, which are electrically connected to a plurality of contact pads 20 disposed on a surface of the package substrate 12 through a plurality of wires 18 and 22 respectively. A package material (not shown) is formed covering the chips 14, 16, the contact pads 14A, 14B, 16A, 16B, the wires 18, 22, and the contact pad 20 disposed on the surface of the package substrate 12. The package 10 is mounted on a print circuit board by bumps (not shown) or leads (not shown) of various sizes to form an electronic system with other active or passive elements to be utilized in consumer electronic devices.

Since consumer electrical devices are tending towards miniaturization, the distance between the chips 14 and 16 of the package 10 will be reduced to decrease the area of the package 10. However, the reduced distance between the chips 14 and 16 results in problems, such as raising the difficulty and complexity in wiring, or electromagnetic interference between the chips 14 and 16.

It is therefore a primary objective of the present invention to provide an interposer for connecting a plurality of chips to overcome the abovementioned wiring difficulty.

According to the present invention, an interposer for connecting a plurality of chips is provided. The interposer has a connective substrate, at least a through via positioned in the connective substrate, and at least a first chip and a second chip. The connective substrate has a first surface and a second surface. The first chip is electrically connected to the first surface, and the second chip is electrically connected to the second surface. Both the first chip and the second chip are flip-chips. The through via acts as a connector and electrically connects the first surface and the second surface of the connective substrate.

The present invention further provides a method of forming an interposer. Initially, a connective substrate having a first surface and a second surface is provided. The first surface includes at least a first dielectric layer, at least a first interconnection, and at least a first contact pad. An adhesive layer is provided to bond the first surface to a carrier. At least a through hole is formed on the second surface, and the through hole penetrates the connective substrate. A conductive layer is formed to fill the through via and to form a through via connecting the first surface and the second surface. Afterwards, at least a second dielectric layer, at least a second interconnection, and at least a second contact pad are formed on the second surface of the connective substrate. In addition, the second interconnection and the second contact pad are electrically connected to the first interconnection and the first contact pad on the first surface. Then, the first surface and the wafer carrier are separated.

The interposer of the present invention is capable of connecting two or more chips, or other components requiring signal transmission. The use of the interposer reduces the area of the package and the size of the electronic systems or barebones having the interposer therein. The interposer is used for several types of packages. Therefore, the interposer overcomes the wiring difficulty and increases the yield of the packaging.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1 is a schematic diagram of a conventional package.

FIGS. 2-10 are schematic diagrams illustrating a method of forming an interposer according to a preferred embodiment of the present invention.

FIG. 11 is a schematic diagram illustrating the interposer for connecting a plurality of chips according to another preferred embodiment of the present invention.

FIG. 12 further discloses the interposers of the present invention connecting three chips according to a preferred embodiment of the present embodiment.

FIG. 13 is a schematic diagram illustrating the interposer connecting several chips in vertical and horizontal directions according to a preferred embodiment of the present invention.

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