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International Business Machines Corporation Dept. 18g patentsThe following is a sampling of recent International Business Machines Corporation Dept. 18g patent applications (USPTO Patent Application #, Patent Title) sorted by month.
July 2009 - International Business Machines Corporation Dept. 18g patents
20090173980 - Providing isolation for wordline passing over deep trench capacitor
20090174008 - Method and structure to protect fets from plasma damage during feol processing
20090174010 - Sram device structure including same band gap transistors having gate stacks with high-k dielectrics and same work function
20090174031 - Dram having deep trench capacitors with lightly doped buried plates
20090174075 - Simultaneous grain modulation for beol applications
20090174084 - Via offsetting to reduce stress under the first level interconnect (fli) in microelectronics packaging
20090175068 - Sram device, and sram device design structure, with adaptable access transistors
20090175325 - System for measuring an eyewidth of a data signal in an asynchronous system
20090175606 - Method and structure to control thermal gradients in semiconductor wafers during rapid thermal processing
20090176339 - Method of multi-port memory fabrication with parallel connected trench capacitors in a cell
20090178024 - Method, computer program product, and system for merging multiple same class instance states
20090167336 - Method and apparatus for dynamic characterization of reliability wearout mechanisms
June 2009 - International Business Machines Corporation Dept. 18g patents
20090164840 - System and method for managing root file system
20090164840 - System and method for managing root file system
20090164885 - Efficient method of migrating lotus domino documents to a non-domino web server, while preserving sections, using portable javascript
20090164885 - Efficient method of migrating lotus domino documents to a non-domino web server, while preserving sections, using portable javascript
20090154263 - Design structure for improving performance of sram cells, sram cell, sram array, and write circuit
20090155715 - Photoresist compositions and method for multiple exposures with multiple layer resist systems
20090157773 - Database management method, apparatus and system
20090146223 - Process and method to lower contact resistance
20090146263 - Structure and method to increase effective mosfet width
20090146316 - Flip-chip assembly with organic chip carrier having mushroom-plated solder resist opening
20090146692 - Structure for apparatus for reduced loading of signal transmission elements
20090148795 - Patterning method using a combination of photolithography and copolymer self-assemblying lithography techniques
20090148986 - Method of making a finfet device structure having dual metal and high-k gates
20090148988 - Method of reducing embedded sige loss in semiconductor device manufacturing
20090149979 - Run-time dispatch system for enhanced product characterization capability
20090150090 - System and method for detection and prevention of influx of airborne contaminants
20090140420 - Soft error rate mitigation by interconnect structure
20090142704 - Method for reducing side lobe printing using a barrier layer
20090143999 - Real time system for monitoring the commonality, sensitivity, and repeatability of test probes
20090144670 - Automated optimization of device structure during circuit design stage
May 2009 - International Business Machines Corporation Dept. 18g patents
20090137109 - Compressive nitride film and method of manufacturing thereof
20090128161 - Structure for robust cable connectivity test receiver for high-speed data receiver
20090128225 - Structure of an apparatus for programming an electronically programmable semiconductor fuse
20090129191 - Structure for sram voltage control for improved operational margins
20090129485 - Structure for transmitter bandwidth optimization circuit
20090132973 - Design structure of an integration circuit and test method of the integrated circuit
20090132982 - Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routes
20090132985 - Design structure for on-chip electromigration monitoring system
20090121270 - Design structure for a trench capacitor
20090121357 - Design structure for bridge of a seminconductor internal node
20090123057 - Method and system for obtaining bounds on process parameters for opc-verification
20090125868 - Multilayer opc for design aware manufacturing
20090115504 - Circuit design methodology to reduce leakage power
20090119357 - Advanced correlation and process window evaluation application
20090119561 - Microcomputer and method of testing the same
April 2009 - International Business Machines Corporation Dept. 18g patents
20090107956 - Thermal gradient control of high aspect ratio etching and deposition processes
20090108306 - Uniform recess of a material in a trench independent of incoming topography
20090108351 - Finfet memory device with dual separate gates and method of operation
20090108364 - Dual workfunction silicide diode
20090108442 - Self-assembled stress relief interface
20090108885 - Design structure for cmos differential rail-to-rail latch circuits
20090109733 - Design structure for sram active write assist for improved operational margins
20090112855 - Method for ordering a search result and an ordering apparatus
20090112963 - Method to perform a subtraction of two operands in a binary arithmetic unit plus arithmetic unit to perform such a method
20090101957 - Simplified method of fabricating isolated and merged trench capacitors
20090101957 - Simplified method of fabricating isolated and merged trench capacitors
20090101957 - Simplified method of fabricating isolated and merged trench capacitors
20090103390 - Three dimensional twisted bitline architecture for multi-port memory
20090103390 - Three dimensional twisted bitline architecture for multi-port memory
20090103390 - Three dimensional twisted bitline architecture for multi-port memory
20090106594 - Method and device for log events processing
20090106594 - Method and device for log events processing
20090106594 - Method and device for log events processing
20090096101 - Bridge for semiconductor internal node
20090090977 - Resistor and fet formed from the metal portion of a mosfet metal gate stack
20090090986 - Fully and uniformly silicided gate structure and method for forming same
20090090993 - Single crystal fuse on air in bulk silicon
20090092810 - Fabrication of soi with gettering layer
20090084183 - Slip ring positive z force liquid isolation fixture permitting zero net force on workpiece
20090084183 - Slip ring positive z force liquid isolation fixture permitting zero net force on workpiece
March 2009 - International Business Machines Corporation Dept. 18g patents
20090083689 - Gridded-router based wiring on a non-gridded library
20090077515 - Method of constrained aggressor set selection for crosstalk induced noise
20090065872 - Full silicide gate for cmos
20090066518 - Id tag package and rfid system
20090070715 - Method for eliminating negative slack in a netlist via transformation and slack categorization
20090058236 - Latch apparatus to an enclosure for an electronic device
20090059057 - Method and apparatus for providing a video image having multiple focal lengths
20090059510 - Drive conversion enclosure
20090059705 - Sram having active write assist for improved operational margins
20090059706 - Sram active write assist method for improved operational margins
February 2009 - International Business Machines Corporation Dept. 18g patents
20090048893 - System and method of role-based calendaring
20090039522 - Bipolar and cmos integration with reduced contact height
20090033355 - Method and apparatus to measure threshold shifting of a mosfet device and voltage difference between nodes
20090037866 - Alternating phase shift mask optimization for improved process window
January 2009 - International Business Machines Corporation Dept. 18g patents
20090026587 - Gradient deposition of low-k cvd materials
20090027075 - System and method of digitally testing an analog driver circuit
20090030543 - Semiconductor manufacturing process monitoring
20090019691 - Micro-electromechanical sub-assembly having an on-chip transfer mechanism
20090014767 - Carbon nanotube conductor for trench capacitors
20090014798 - Finfet sram with asymmetric gate and method of manufacture thereof
20090019326 - Self-synchronizing bit error analyzer and circuit
20090013290 - Method and system for electromigration analysis on signal wiring
20090001465 - Method of forming a guard ring or contact to an soi substrate
20090001466 - Method of forming an soi substrate contact
20090002960 - Apparatus for retaining a computer card
20090004978 - Transmitter bandwidth optimization circuit
20090005896 - Manufacturing work in process management system
October 2008 - International Business Machines Corporation Dept. 18g patents
20080257597 - Printed circuit board manufacturing method and printed circuit board
20080263488 - Method for generating a skew schedule for a clock distribution network containing gating elements
20080263553 - Dynamic service level manager for image pools
20080253404 - Dynamic time division multiplexing circuit without a shadow table
20080254624 - Metal cap for interconnect structures
20080246069 - Folded node trench capacitor
20080246093 - Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern
20080236617 - Use of dilute hydrochloric acid in advanced interconnect contact clean in nickel semiconductor technologies
20080237709 - After gate fabrication of field effect transistor having tensile and compressive regions
20080237737 - Overlapped stressed liners for improved contacts
20080237749 - Cmos gate conductor having cross-diffusion barrier
September 2008 - International Business Machines Corporation Dept. 18g patents
20080230822 - Vertical trench memory cell with insulating ring
20080230891 - Chip and wafer integration process using vertical connections
20080231312 - Structure for modeling stress-induced degradation of conductive interconnects
20080233366 - Structure and method for sicoh interfaces with increased mechanical strength
20080233514 - Positive photoresist composition with a polymer including a fluorosulfonamide group and process for its use
20080224255 - Subground rule sti fill for hot structure
20080224328 - Temporary chip attach using injection molded solder
20080225251 - Immersion optical lithography system having protective optical coating
20080227030 - Use of mixed bases to enhance patterned resist profiles on chrome or sensitive substrates
20080217612 - Structure and method of mapping signal intensity to surface voltage for integrated circuit inspection
20080217665 - Semiconductor device structure having enhanced performance fet device
20080217731 - interconnect structure with dielectric air gaps
20080217777 - Embedded barrier for dielectric encapsulation
20080218054 - Carbon tube for electron beam application
20080215175 - Available to promise allocation optimization tool
20080215554 - Data plotting extension for structured query language
August 2008 - International Business Machines Corporation Dept. 18g patents
20080209376 - System and method for sign-off timing closure of a vlsi chip
20080209378 - Method and system for prototyping electronic devices with multi-configuration chip carriers
20080197500 - Interconnect structure with bi-layer metal cap
20080197513 - Beol interconnect structures with improved resistance to stress
20080201684 - Simulation site placement for lithographic process models
20080191281 - Stressed soi fet having tensile and compressive device regions
20080191284 - Method for improved fabrication of a semiconductor using a stress proximity technique process
20080191788 - Soi mosfet device with adjustable threshold voltage
20080185583 - Structure and method for monitoring and characterizing pattern density dependence on thermal absorption in a semiconductor manufacturing process
20080185626 - Trench capacitor and method for fabricating the same
20080185657 - Dual stress liner
20080187079 - Data recovery circuits using oversampling for best data sample selection
July 2008 - International Business Machines Corporation Dept. 18g patents
20080180139 - Cmos differential rail-to-rail latch circuits
20080182402 - Sub-lithographic interconnect patterning using self-assembling polymers
20080182490 - Method and system for pad conditioning in an ecmp process
20080173950 - Structure and method of fabricating electrical structure having improved charge mobility
20080173976 - Air gap under on-chip passive device
20080174334 - Method for prediction of premature dielectric breakdown in a semiconductor
20080176365 - Method of making double-gated self-aligned finfet having gates of different lengths
20080178129 - Comparator circuit and method for operating a comparator circuit
20080169508 - Stressed soi fet having doped glass box layer
20080169528 - Subground rule sti fill for hot structure
20080169529 - Efuse containing sige stack
20080170457 - Method for sensing a signal in an integrated circuit complementary fuse arrangement
20080172392 - Method, system, and computer program product for data upload in a computing system
20080172576 - Method for enhancing the diagnostic accuracy of a vlsi chip
20080164494 - Bipolar transistor with silicided sub-collector
20080164540 - Method and apparatus for forming nickel silicide with low defect density in fet devices
20080164558 - Method for fabricating shallow trench isolation structures using diblock copolymer patterning
20080166568 - Top coat material and use thereof in lithography processes
20080166847 - Method of forming source and drain of field-effect-transistor and structure thereof
20080156265 - Method and apparatus for forming nickel silicide with low defect density in fet devices
20080156636 - Homogeneous copper interconnects for beol
20080157077 - Integrated circuit and methods of measurement and preparation of measurement structure
20080157269 - Reversible electric fuse and antifuse structures for semiconductor devices
20080158564 - Monitoring a photolithographic process using a scatterometry target
20080163242 - Information processing apparatus, method, and program for controlling resource access by application program
June 2008 - International Business Machines Corporation Dept. 18g patents
20080150033 - Scalable strained fet device and method of fabricating the same
20080150087 - Semiconductor chip shape alteration
20080153296 - Method of formation of a damascene structure utilizing a protective film
20080145793 - High resolution imaging process using an in-situ image modifying layer
20080146181 - Design structure for data communications systems
20080135987 - Gate conductor structure
20080137721 - Automatic adaptive equalization method for high-speed serial transmission link
20080138631 - Method to reduce mechanical wear of immersion lithography apparatus
20080140247 - Method and system of data weighted object orientation for data mining
20080141211 - Opc verification using auto-windowed regions
20080128771 - Nano-fuse structural arrangements having blow protection barrier spaced from and surrounding fuse link
20080129324 - Hot switchable voltage bus for iddq current measurements
20080129329 - Method of testing connectivity using dual operational mode cml latch
20080130200 - Integrated circuit comb capacitor
20080132070 - Fully and uniformly silicided gate structure and method for forming same
20080134117 - System and method for efficient analysis of point-to-point delay constraints in static timing
May 2008 - International Business Machines Corporation Dept. 18g patents
20080122026 - Structure for creation of a programmable device
20080122045 - Dual liner capping layer interconnect structure
20080122103 - Embedded nano uv blocking barrier for improved reliability of copper/ultra low k interlevel dielectric electronic devices
20080123442 - Method to improve performance of sram cells, sram cell, sram array, and write circuit
20080124818 - Method and system for reducing the variation in film thickness on a plurality of semiconductor wafers having multiple deposition paths in a semiconductor manufacturing process
20080127019 - Method and system for designing a memory register
20080127027 - Printability verification by progressive modeling accuracy
20080127029 - Closed-loop design for manufacturability process
20080116524 - Dual stress liner
20080111200 - Forming conductive stud for semiconductive devices
20080111202 - Forming conductive stud for semiconductive devices
20080115029 - iterative test generation and diagnostic method based on modeled and unmodeled faults
20080107149 - Method for monitoring stress-induced degradation of conductive interconnects
20080108186 - Method of providing protection against charging damage in hybrid orientation transistors
20080109267 - Online startup of an innovation project
20080109780 - Method of and apparatus for optimal placement and validation of i/o blocks within an asic
20080102400 - Negative tone silicon-containing resist for e-beam lithography
20080102569 - Method of fabricating vertical body-contacted soi transistor
20080102599 - Reduced leakage interconnect structure
20080104595 - Method for enhancing efficiency in mutual exclusion
April 2008 - International Business Machines Corporation Dept. 18g patents
20080092367 - Micro-cavity mems device and method of fabricating same
20080087961 - Method of reducing stacking faults through annealing
20080088026 - Enhanced interconnect structure
20080088027 - Dry etchback of interconnect contacts
20080089116 - Sram voltage control for improved operational margins
20080089159 - Apparatus and method for programming an electronically programmable semiconductor fuse
20080083963 - P-i-n semiconductor diodes and methods of forming the same
20080085585 - Structure and method for creation of a transistor
20080079176 - Method and structure to enhance temperature/humidity/bias performance of semiconductor devices by surface modification
20080080778 - Image data compression method and apparatuses, image display method and apparatuses
March 2008 - International Business Machines Corporation Dept. 18g patents
20080067369 - High-resolution optical channel for non-destructive navigation and processing of integrated circuits
20080067631 - Creating increased mobility in a bipolar device
20080069494 - Electro-optical module comprising flexible connection cable and method of making the same
20080071852 - Method to perform a subtraction of two operands in a binary arithmetic unit plus arithmetic unit to perform such a method
20080072111 - Method for performing a test case with a lbist engine on an integrated circuit, integrated circuit and method for specifying an integrated circuit
20080061825 - Cml to cmos signal converter
20080064172 - Stressed semiconductor device structures having granular semiconductor material
20080054326 - Low resistance contact structure and fabrication thereof
20080054392 - Bridge for semiconductor internal node
20080054413 - Self-aligned dual segment liner and method of manufacturing the same
20080059019 - Method and system for on-board automotive audio recorder
February 2008 - International Business Machines Corporation Dept. 18g patents
20080048729 - Comparator circuit and method for operating a comparator circuit
20080045039 - Method of forming nitride films with high compressive stress for improved pfet device performance
20080036007 - Method of forming nitride films with high compressive stress for improved pfet device performance
20080036598 - Tamper-proof structures for protectig electronic modules
20080037339 - Memory array for an integrated circuit
20080037340 - Apparatus for testing a memory of an integrated circuit
20080037341 - Enabling memory redundancy during testing
20080037690 - Data communications systems
20080038676 - Top coat material and use thereof in lithography processes
20080033589 - Data mining to detect performance quality of tools used repetitively in manufacturing
20080034339 - Pattern matching system for layout shapes using walsh patterns
January 2008 - International Business Machines Corporation Dept. 18g patents
20080023778 - Fully silicided gate electrodes and method of making the same
20080024781 - Optical spot geometric parameter determination using calibration targets
20080026522 - High performance cmos device structures and method of manufacture
20080026566 - Dual damascene interconnect structures having different materials for line and via conductors
20080026568 - Interconnect structure and process of making the same
20080027932 - Apparatus of generating browsing paths for data and method for browsing data
20080028357 - Method of automatic generation of micro clock gating for reducing power consumption
20080017223 - Conductive adhesive rework method
20080017984 - Blm structure for application to copper pad
20080020327 - Method of formation of a damascene structure
20080020531 - Semiconductor devices having torsional stresses
20080011814 - Method and system for self-aligning parts in mems
20080014663 - Structure and method of fabricating a hinge type mems switch
20080014731 - An interconnect structure with dielectric air gaps
20080006902 - A mosfet fuse programmed by electromigration
20080000536 - Method and device for flowing a liquid on a surface
20080004741 - Available to promise allocation optimization tool
20080005709 - Verification of logic circuits using cycle based delay models
December 2007 - International Business Machines Corporation Dept. 18g patents
20070295231 - Apparatus and method for cleaning stencils employed in a screen printing apparatus
20070296001 - Multiple conduction state devices having differently stressed liners
20070296947 - Immersion optical lithography system having protective optical coating
20070299826 - Method and apparatus for establishing relationship between documents
20070289896 - Method for packaging contamination vulnerable articles and package therefore
20070284693 - Electrically programmable fuse with asymmetric structure
20070284736 - Enhanced mechanical strength via contacts
20070287367 - Extended life conditioning disk
November 2007 - International Business Machines Corporation Dept. 18g patents
20070273004 - Like integrated circuit devices with different depth
20070277131 - Method for a fast incremental calculation of the impact of coupled noise on timing
20070267463 - Apparatus for mounting columns for grid array electronic packages
20070269928 - Temporary chip attach using injection molded solder
20070269942 - Dual stress liner
20070269992 - Compressive nitride film and method of manufacturing thereof
20070270536 - Conductive adhesive composition
20070262416 - Method and structure for creation of a metal insulator metal capacitor
20070262475 - Polysilicon hard mask for enhanced alignment signal
20070259162 - Film stack having under layer for preventing pinhole defects
20070259489 - Method of forming transistor structure having stressed regions of opposite types
20070261013 - Designer's intent tolerance bands for proximity correction and checking
20070252287 - Integrated electronic chip and interconnect device and process for making the same
20070252613 - Universal cmos device leakage characterization system
20070254430 - A trench capacitor and method for fabricating the same
20070255440 - Method and system for improved performance of manufacturing processes
20070255836 - Agent allocation program, method and apparatus
October 2007 - International Business Machines Corporation Dept. 18g patents
20070249112 - Differential spacer formation for a field effect transistor
20070249114 - Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions
20070249126 - A structure and method for fabrication of deep junction silicon-on-insulator transistors
20070249144 - Method of forming silicon-on-insulator wafer having reentrant shape dielectric trenches
20070249174 - Patterning sub-lithographic features with variable widths
20070242548 - Programmable semiconductor device
20070243333 - Method of forming film stack having under layer for preventing pinhole defects
20070235769 - Structure and method for thermally stressing or testing a semiconductor device
20070238267 - Epitaxy of silicon-carbon substitutional solid solutions by ultra-fast annealing of amorphous material
20070228479 - Protection against charging damage in hybrid orientation transistors
20070230150 - Power supply structure for high power circuit packages
20070233494 - Method and system for generating sound effects interactively
September 2007 - International Business Machines Corporation Dept. 18g patents
20070221401 - Releasably mountable electronics component
20070222015 - Trench photodetector
20070222081 - Surface treatment of inter-layer dielectric
20070224824 - Method of repairing process induced dielectric damage by the use of gcib surface treatment using gas clusters of organic molecular species
20070226664 - Method and system for verifying the equivalence of digital circuits
20070215842 - Manufacturable cowp metal cap process for copper interconnects
20070215978 - Tuneable semiconductor device
20070218625 - Trench metal-insulator-metal (mim) capacitors integrated with middle-of-line metal contacts, and method of fabricating same
20070220476 - Multilayer opc for design aware manufacturing
20070212863 - Double exposure double resist layer process for forming gate patterns
20070208964 - Method and apparatus for dynamic system-level frequency scaling
August 2007 - International Business Machines Corporation Dept. 18g patents
20070200605 - Dual operational mode cml latch
20070203774 - Vendor managed inventory liability tracking automation
20070204244 - Method for testing the validity of initial-condition statements in circuit simulation, and correcting inconsistencies thereof
20070194387 - Extended raised source/drain structure for enhanced contact area and method for forming extended raised source/drain structure
20070189057 - Multiple port memory having a plurality of parallel connected trench capacitors in a cell
20070190697 - Electrically programmable fuse for silicon-on-insulator (soi) technology
20070190713 - Cmos gate structures fabricated by selective oxidation
20070181930 - Structure and method of making double-gated self-aligned finfet having gates of different lengths
July 2007 - International Business Machines Corporation Dept. 18g patents
20070164397 - Process for forming a buried plate
20070164768 - On-chip electromigration monitoring system
20070166648 - Integrated lithography and etch for dual damascene structures
20070166995 - Method for direct electroplating of copper onto a non-copper plateable layer
20070166996 - Method of making a semiconductor structure with a plating enhancement layer
20070158395 - Method for preparing and assembling a soldered substrate
20070158714 - One-mask high-k metal-insulator-metal capacitor integration in copper back-end-of-line processing
20070158717 - Integrated circuit comb capacitor
20070158753 - Semiconductor device structure having low and high performance devices of same conductive type on same substrate
20070158851 - Method to improve time dependent dielectric breakdown
20070160448 - Receipt and delivery control system for front opening unified and reticle storage pods
20070155186 - Optimized sicn capping layer
June 2007 - International Business Machines Corporation Dept. 18g patents
20070143719 - Synthesizing current source driver model for analysis of cell characteristics
20070126412 - Waveform measuring apparatus and method thereof
20070128010 - An apparatus for pod transportation within a semiconductor fabrication facility
20070128784 - Method and structure for buried circuits and devices
20070128840 - Method of forming thin sgoi wafers with high relaxation and low stacking fault defect density
20070128859 - Combined stepper and deposition tool
May 2007 - International Business Machines Corporation Dept. 18g patents
20070120197 - Method and structure for enhancing both nmosfet and pmosfet performance wth a stressed film
20070121370 - Sram voltage control for improved operational margins
20070122956 - Transistor with dielectric stressor element fully underlying the active semiconductor region
20070122961 - Method and structure for enhancing both nmosfet and pmosfet performance with a stressed film
20070122982 - Method of applying stresses to pfet and nfet transistor channels for improved performance
20070124635 - Integration circuit and test method of the same
20070114605 - Ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formation
20070114632 - Transistor having dielectric stressor elements at different depths from a semiconductor surface for applying shear stress
20070115018 - Structure and method for monitoring stress-induced degradation of conductive interconnects
20070108984 - Ionization test for electrical verification
20070105029 - Differential critical dimension and overlay metrology apparatus and measurement method
20070106972 - Method for fabricating integrated circuit features
20070096215 - Transistor with dielectric stressor elements
20070096223 - Transistor having dielectric stressor elements for applying in-plane shear stress
20070096259 - Fabrication of bipolar transistor having reduced collector-base capacitance
20070099346 - Surface treatments for underfill control
20070099360 - Integrated circuits having strained channel field effect transistors and methods of making
20070099416 - Shrinking contact apertures through lpd oxide
April 2007 - International Business Machines Corporation Dept. 18g patents
20070085134 - Semiconductor memory device with increased node capacitance
20070087593 - Structure for monitoring semiconductor polysilicon gate profile
20070080440 - Soi device with different crystallographic orientations
20070083847 - Designer's intent tolerance bands for proximity correction and checking
20070076179 - Immersion optical lithography system having protective optical coating
20070077702 - Trench memory cell and method for making the same
20070077753 - Fabrication of via contacts having dual silicide layers
20070077760 - Method and apparatus for forming nickel silicide with low defect density in fet devices
February 2007 - International Business Machines Corporation Dept. 18g patents
20070034967 - Metal gate mosfet by full semiconductor metal alloy conversion
20070037100 - High aspect ratio mask open without hardmask
20070037325 - After deposition method of thinning film to reduce pinhole defects
20070038865 - Tamper-proof caps for large assembly
20070032055 - Dry etchback of interconnect contacts
20070023864 - Methods of fabricating bipolar transistor for improved isolation, passivation and critical dimension control
January 2007 - International Business Machines Corporation Dept. 18g patents
20070007323 - Standoff structures for surface mount components
20070007548 - Method of forming nitride films with high compressive stress for improved pfet device performance
20070009148 - Optical surface inspection
20070010050 - Method for forming semiconductor devices having reduced gate edge leakage current
20070010081 - Mosfet with multiple fully silicided gate and method for making the same
20070010093 - Method of room temperature growth of siox on silicide as an etch stop layer for metal contact open of semiconductor devices
20070010097 - Apparatus and method for selected site backside unlayering of silicon, gaas, gaxalyasz of soi technologies for scanning probe microscopy and atomic force probing characterization
20070011534 - Self-synchronising bit error analyser and circuit
20070002845 - Multi-channel synchronization architecture
20070003128 - A method of aligning a pattern on a workpiece
December 2006 - International Business Machines Corporation Dept. 18g patents
20060290922 - Apparatus and method for color filter inspection
20060292779 - Structure and method for making strained channel field effect transistor using sacrificial spacer
20060292789 - Structure and method for collar self-aligned to buried plate
20060292852 - Back end interconnect with a shaped interface
20060285411 - Single cycle refresh of multi-port dynamic random access memory (dram)
20060285420 - Three dimensional twisted bitline architecture for multi-port memory
20060278932 - Secure electrically programmable fuse
20060278998 - Integrated electronic chip and interconnect device and process for making the same
20060281224 - Compliant passivated edge seal for low-k interconnect structures
20060281338 - Method for prediction of premature dielectric breakdown in a semiconductor
20060273169 - A system for secure and accurate electronic voting
20060273372 - Lateral lubistor structure and method
20060273393 - Structure and method of making field effect transistor having multiple conduction states
20060273841 - Programming and determining state of electrical fuse using field effect transistor having multiple conduction states
20060274681 - Apparatus and method for reduced loading of signal transmission elements
November 2006 - International Business Machines Corporation Dept. 18g patents
20060270192 - Semiconductor substrate and device with deuterated buried layer
20060271680 - method for transmitting window probe packets
20060271905 - Optical proximity correction using progressively smoothed mask shapes
20060261477 - Method of forming contact for dual liner product
20060261480 - Method of fabricating strained channel field effect transistor pair having underlapped dual liners
20060261921 - Multilayer coil assembly and method of production
20060263975 - Method for making a trench memory cell
20060264048 - Interconnect structure diffusion barrier with high nitrogen content
20060255415 - Structure and method of making a field effect transistor having an asymmetrically stressed channel region
20060255461 - Handling and positioning of metallic plated balls for socket application in ball grid array packages
20060257792 - A method of structuring of a substrate
20060258073 - Method for forming a sige or sigec gate selectively in a complementary mis/mos fet device
20060248141 - Dynamically configurable fault tolerance in autonomic computing with multiple service points
October 2006 - International Business Machines Corporation Dept. 18g patents
20060242506 - High-speed level sensitive scan design test scheme with pipelined test clocks
20060234401 - Early detection test for identifying defective semiconductor wafers in a front-end manufacturing line
20060236039 - Method and apparatus for synchronizing shared data between components in a group
20060236236 - System and method for monitoring computer user input
20060236278 - Method of automatic generation of micro clock gating for reducing power consumption
20060226537 - Multilayer circuit board and method of manufacturing the same
20060220737 - High q monolithic inductors for use in differential circuits
20060221827 - Tcp implementation with message-count interface
20060221946 - Connection establishment on a tcp offload engine
September 2006 - International Business Machines Corporation Dept. 18g patents
20060202249 - Simplified buried plate structure and process for semiconductor-on-insulator chip
20060196917 - Method and device for pressure welding, which takes into account deviations in the length of workpieces
20060197179 - Dense semiconductor fuse array
20060197183 - Improved mim capacitor structure and process
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