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International Business Machines Corporation Dept. 18g patentsThe following is a sampling of recent International Business Machines Corporation Dept. 18g patent applications (USPTO Patent Application #, Patent Title) sorted by month.
February 2011 - International Business Machines Corporation Dept. 18g patents
20110037143 - Semiconductor device using an aluminum interconnect to form through-silicon vias
20110034021 - Programmable through silicon via
20110027948 - Method for manufacturing a finfet device
January 2011 - International Business Machines Corporation Dept. 18g patents
20110018575 - Method and system for assessing reliability of integrated circuit
20110014757 - Process integration for flash storage element and dual conductor complementary mosfets
20110016442 - Method of performing static timing analysis considering abstracted cell's interconnect parasitics
20110001169 - Forming uniform silicide on 3d structures
December 2010 - International Business Machines Corporation Dept. 18g patents
20100327430 - Semiconductor device assembly having a stress-relieving buffer layer
20100327445 - Structure of power grid for semiconductor devices and method of making the same
20100330763 - Method of creating asymmetric field-effect-transistors
20100332193 - Method of multi-segments modeling bond wire interconnects with 2d simulations in high speed, high density wire bond packages
20100314689 - Local metallization and use thereof in semiconductor devices
20100301331 - Body contact structure for in-line voltage contrast detection of pfet silicide encroachment
20100306603 - Segmented and overlapped skew tracking method for serdes frame interface level 5
20100306723 - Order independent method of performing statistical n-way maximum/minimum operation for non-gaussian and non-linear distributions
November 2010 - International Business Machines Corporation Dept. 18g patents
20100289144 - 3d integration structure and method using bonded metal planes
20100289645 - System and method for safeguarding wafers and photomasks
20100283089 - Method of reducing stacking faults through annealing
20100277210 - Three-dimensional chip-stack synchronization
20100281447 - Method for detecting contradictory timing constraint conflicts
October 2010 - International Business Machines Corporation Dept. 18g patents
20100265778 - Semiconductor memory device
20100269083 - Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of vlsi circuits
20100258904 - Bottle-shaped trench capacitor with enhanced capacitance
20100261318 - 3d chip-stack with fuse-type through silicon via
20100255428 - Method to mitigate resist pattern critical dimension variation in a double-exposure process
September 2010 - International Business Machines Corporation Dept. 18g patents
20100244198 - Cmos sige channel pfet and si channel nfet devices with minimal sti recess
20100244206 - Method and structure for threshold voltage control and drive current improvement for high-k metal gate transistors
August 2010 - International Business Machines Corporation Dept. 18g patents
20100207213 - Body contacts for fet in soi sram array
20100207245 - Highly scalable trench capacitor
20100207246 - Method of making an mim capacitor and mim capacitor structure formed thereby
20100210098 - Self-aligned contact
20100211922 - Method of performing statistical timing abstraction for hierarchical timing analysis of vlsi circuits
20100200896 - Embedded stress elements on surface thin direct silicon bond substrates
20100200949 - Method for tuning the threshold voltage of a metal gate and high-k device
20100200958 - Pedestal guard ring having continuous m1 metal barrier connected to crack stop
20100200960 - Deep trench crackstops under contacts
20100201376 - Detecting asymmetrical transistor leakage defects
20100201390 - Probe card, method for manufacturing probe card, and prober apparatus
20100203717 - Cut first methodology for double exposure double etch integration
20100204839 - Method and apparatus for the monitoring of water usage with pattern recognition
20100204940 - Method and system of commonality analysis for lots with scrapped wafer
20100193964 - method of making 3d integrated circuits and structures formed thereby
20100194482 - Compensation of vco gain curve offsets using auto-calibration
20100194483 - Auto-calibration for ring oscillator vco
20100196825 - Developable bottom antireflective coating compositions especially suitable for ion implant applications
July 2010 - International Business Machines Corporation Dept. 18g patents
20100187610 - Semiconductor device having dual metal gates and method of manufacture
20100187643 - Method for tuning the threshold voltage of a metal gate and high-k device
20100181643 - Efuse with partial sige layer and design structure therefor
20100182040 - Programmable through silicon via
20100182041 - 3d chip-stack with fuse-type through silicon via
20100182729 - Method of operating transistors and structures thereof for improved reliability and lifetime
20100185999 - Short path customized mask correction
20100176450 - Structure and method of forming a transistor with asymmetric channel and source/drain regions
20100176506 - Thermoelectric 3d cooling
20100176512 - Structure and method for back end of the line integration
20100176513 - Structure and method of forming metal interconnect structures in ultra low-k dielectrics
20100176514 - Interconnect with recessed dielectric adjacent a noble metal cap
20100177179 - Apparatus and method for enhancing field of vision of the visually impaired
20100178615 - Method for reducing tip-to-tip spacing between lines
20100178619 - Method for enhancing lithographic imaging of isolated and semi-isolated features
20100180056 - Bus access control apparatus and method
20100180242 - Method and system for efficient validation of clock skews during hierarchical static timing analysis
20100180243 - Method of performing timing analysis on integrated circuit chips with consideration of process variations
20100180244 - Method for efficiently checkpointing and restarting static timing analysis of an integrated circuit chip
20100171031 - Calibration of lithographic process models
20100171036 - Opc model calibration process
20100173247 - Substrate planarization with imprint materials and processes
20100174957 - Correlation and overlay of large design physical partitions and embedded macros to detect in-line defects
20100175040 - Methodology of placing printing assist feature for random mask layout
20100175041 - Adjustment of mask shapes for improving printability of dense integrated circuit layout
20100175042 - Efficient isotropic modeling approach to incorporate electromagnetic effects into lithographic process simulations
20100175043 - Fast and accurate method to simulate intermediate range flare effects
June 2010 - International Business Machines Corporation Dept. 18g patents
20100149723 - Method and structure for creation of a metal insulator metal capacitor
20100140674 - Mosfet with multiple fully silicided gate and method for making the same
20100146210 - Method to verify an implemented coherency algorithm of a multi processor environment
May 2010 - International Business Machines Corporation Dept. 18g patents
20100109119 - Method of forming a guard ring or contact to an soi substrate
April 2010 - International Business Machines Corporation Dept. 18g patents
20100101638 - Using 3d integrated diffractive gratings in solar cells
20100102373 - Trench memory with self-aligned strap formed by self-limiting process
20100103433 - Differential critical dimension and overlay metrology apparatus and measurement method
20100096744 - Printed wiring board and method for manufacturing the same
20100090288 - Method of forming source and drain of a field-effect-transistor and structure thereof
20100080446 - Inline low-damage automated failure analysis
March 2010 - International Business Machines Corporation Dept. 18g patents
20100061156 - Method of controlling memory and memory system thereof
February 2010 - International Business Machines Corporation Dept. 18g patents
20100038751 - Structure and method for manufacturing trench capacitance
20100038777 - Method of making a sidewall-protected metallic pillar on a semiconductor substrate
20100038790 - reliability of wide interconnects
20100039191 - Active inductor for asic application
20100042955 - Method of minimizing early-mode violations causing minimum impact to a chip design
20100042991 - Business-in-a-box integration server and integration method
20100029082 - Method and apparatus for angular high density plasma chemical vapor deposition
January 2010 - International Business Machines Corporation Dept. 18g patents
20100019354 - Semiconductor chip shape alteration
20100022088 - Multiple exposure and single etch integration method
20100013446 - method for controlling the supply voltage for an integrated circuit and an apparatus with a voltage regulation module and an integrated circuit
20100006985 - Formation of soi by oxidation of silicon with engineered porosity gradient
20100009161 - Structure and method for sicoh interfaces with increased mechanical strength
20100003800 - Bipolar transistor with silicided sub-collector
20100005440 - Calibration and verificataion structures for use in optical proximity correction
December 2009 - International Business Machines Corporation Dept. 18g patents
20090315124 - Work function engineering for edram mosfets
20090306807 - Multidimensional process window optimization in semiconductor manufacturing
20090294872 - Ge/xe implants to reduce junction capacitance and leakage
20090297759 - Stress locking layer for reliable metallization
20090299679 - Method of adaptively selecting chips for reducing in-line testing in a semiconductor manufacturing line
20090300562 - Design structure for out of band signaling enhancement for high speed serial driver
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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with International Business Machines Corporation Dept. 18g in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for International Business Machines Corporation Dept. 18g with additional patents listed. Browse our Agent directory for other possible listings.
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