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Interconnection pattern designUSPTO Application #: 20070165388Title: Interconnection pattern design Abstract: An interconnection pattern design, which has an improved reliability under mechanical shock and thermal cycling loads. A semiconductor component comprises a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the pattern has substantially rounded or chamfered corners. The present invention provides an improved interconnection life and reliability of ball grid array packages and it is easily implemented. (end of abstract)
USPTO Applicaton #: 20070165388 - Class: 361760000 (USPTO)
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