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09/07/06 - USPTO Class 438 |  144 views | #20060199368 | Prev - Next | About this Page  438 rss/xml feed  monitor keywords

Interconnect arrangement and associated production methods

Title: Interconnect arrangement and associated production methods


Related Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Contacting Multiple Semiconductive Regions (i.e., Interconnects), Air Bridge Structure

Brief Patent Description - Full Patent Description - Patent Claims

The Patent Description & Claims data below is from USPTO Patent Application 20060199368, Interconnect arrangement and associated production methods.


1. An interconnect arrangement comprising: an electrically conductive mount substrate; a dielectric layer formed on the mount substrate; and an electrically conductive interconnect formed on the dielectric layer, wherein at least a portion of the dielectric layer under the interconnect contains a cavity.

2. The interconnect arrangement of claim 1, further comprising a porous dielectric layer that adheres to the interconnect and bounds the cavity.

3. The interconnect arrangement of claim 1, wherein the interconnect comprises a contact via that leads from the interconnect to a surface of the substrate and electrically connects to the substrate.

4. The interconnect arrangement of claim 1, wherein the interconnect comprises a dummy contact via that leads from the interconnect to a surface of the substrate and does not electrically connect to the substrate.

5. The interconnect arrangement of claim 1, wherein the interconnect comprises a barrier layer that prevents interconnect material from diffusing into the mount substrate.

6. The interconnect arrangement of claim 1, further comprising a residual decomposition layer formed in the cavity on a surface of the mount substrate.

7. An interconnect arrangement comprising: an electrically conductive mount substrate; a dielectric layer formed on the mount substrate; an electrically conductive interconnect formed on the dielectric layer, at least a portion of the dielectric layer under the interconnect contains a cavity; and dielectric supporting elements formed in the cavity on a surface of the mount substrate, the dielectric supporting elements support the interconnect.

8. The interconnect arrangement of claim 7, further comprising a non-porous dielectric covering layer formed on the interconnect such that the cavity is also located to a side of the interconnect.

9. The interconnect arrangement of claim 7, wherein the supporting elements are formed in a straight line and essentially at right angles to the interconnect.

10. The interconnect arrangement of claim 7, wherein the supporting elements comprise islands.

11. A method for production of an interconnect arrangement, the method comprising: a) forming a sacrificial layer on an electrically conductive mount substrate; b) forming an interconnect layer on the sacrificial layer; c) structuring the interconnect layer and the sacrificial layer to produce a structured interconnect on the structured sacrificial layer; d) forming a porous dielectric layer on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer; and e) removing the sacrificial layer to form a cavity under the interconnect.

12. The method of claim 11, wherein, in a), an opening for a contact via or a dummy contact via is formed in the sacrificial layer.

13. The method of claim 11, wherein, in a) to c), a damascene or dual damascene process is carried out.

14. The method of claim 11, wherein, in e) thermal conversion of the sacrificial layer is carried out in a temperature range from 300 to 600 degrees Celsius, with the gaseous decomposition products escaping through the porous layer.

15. The method of claim 11, wherein, in e), a residual decomposition layer is formed on the surface of the mount substrate.

16. A method for production of an interconnect arrangement, the method comprising: a) forming a supporting structure on a mount substrate; b) forming a sacrificial layer on a surface of the mount substrate and of the supporting structure; c) planarizing the sacrificial layer to expose the surface of the supporting structure; d) forming an interconnect layer on the surface of the sacrificial layer and of the supporting structure; e) structuring the interconnect layer to produce a structured interconnect; f) removing the sacrificial layer to form a cavity at least under the interconnect; and g) forming a closed dielectric covering layer above the interconnect.

17. The method of claim 17, wherein, after e), an opening for a contact via or a dummy contact via is formed in the sacrificial layer.

18. The method of claim 17, wherein, in f), thermal conversion of the sacrificial layer is carried out in a temperature range from 300 to 600 degrees Celsius.

19. The method of claim 17, wherein, in f), a residual decomposition layer is formed on the surface of the mount substrate.

20. The method of claim 17, wherein, in a), the supporting structure is formed in a linear form or like islands.

21. An interconnect arrangement comprising: an electrically conductive mount substrate; means for insulating the mount substrate, at least a portion of the means comprising a cavity; and means for electrically interconnecting elements formed on the insulating means.

22. The interconnect arrangement of claim 21, further comprising porous means for bounding the cavity.

23. The interconnect arrangement of claim 21, wherein the interconnect means comprises barrier means for preventing interconnect material from diffusing into the mount substrate during fabrication.

24. The interconnect arrangement of claim 21, further comprising residual decomposition means for permitting gaseous decomposition products created during fabrication to escape from the interconnect arrangement.

25. The interconnect arrangement of claim 21, further comprising support means for supporting the interconnect means.

Brief Patent Description - Full Patent Description - Patent Claims

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Semiconductor device and manufacturing method thereof
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Ribs for line collapse prevention in damascene structures
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