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Interconnect arrangement and associated production methodsRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Contacting Multiple Semiconductive Regions (i.e., Interconnects), Air Bridge StructureInterconnect arrangement and associated production methods description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060199368, Interconnect arrangement and associated production methods. Brief Patent Description - Full Patent Description - Patent Application Claims
PRIORITY CLAIM [0001] This application claims priority to German Patent Application DE 10 2005 008 476.1, filed on Feb. 24, 2005, which is incorporated by reference in their entirety. TECHNICAL FIELD [0002] The present invention relates to an interconnect arrangement and to associated production methods, and in particular to an interconnect arrangement with improved electrical characteristics as can be used as a bit line in a DRAM memory cell. BACKGROUND [0003] In semiconductor technology, interconnect arrangements are used to form wiring for semiconductor components. In this case, a dielectric layer or insulating layer is normally formed on an electrically conductive mount substrate, such as a semiconductor substrate, and an electrically conductive interconnect layer is formed on this dielectric layer, with the interconnect layer representing the final interconnect, after structuring. Further insulating layers and electrically conductive layers are then formed successively, thus resulting in a layer stack which allows even complex wiring structures. [0004] The electrical characteristics of the interconnect arrangement in this case depend primarily on the materials used and in particular on the electrical conductivity of the interconnects, as well on parasitic capacitances per area section or length section of the interconnect. [0005] Particularly in semiconductor memory cells such as DRAM memory cells, stored information is transported via a bit line to an evaluation circuit. FIG. 12 shows a simplified equivalent circuit of a conventional DRAM memory cell in which a storage capacitor CS is connected via a selection transistor AT to a bit line BL. The storage capacitor CS can be a trench capacitor or an MIM (metal-insulator-metal) capacitor. The selection transistor AT can be actuated via a word line WL such that the charge or information stored in the storage capacitor CS can be read via the bit line BL. The electrical characteristics of the bit line are determined primarily by their length 1 and the conductivity per unit length, and the parasitic capacitance CP per unit length and/or unit area. As shown in FIG. 12, the parasitic capacitance CP is charged and discharged with the charge stored in the storage capacitor CS of the memory cell. To attenuate the original signal as little as possible, the parasitic capacitance of the bit line as well as a parasitic line resistance (which is not illustrated) is minimized. To achieve this minimization, the length of the bit lines is optimized. [0006] U.S. Pat. No. 5,461,003 filed on May 27, 1994 and issued on Oct. 24, 1995 discloses an interconnect arrangement in which air gaps or non-conductive gases or a vacuum are/is used to reduce the capacitive coupling between adjacent interconnects. In this case, a porous dielectric covering layer was used for the removal of a sacrificial layer used for the air gap, while at the same time ensuring sufficient mechanical robustness. However, further improvements in the electrical characteristics are obtained. BRIEF DESCRIPTION OF THE DRAWINGS [0007] The present invention is illustrated by way of example and not limited to the accompanying figures in which like references indicate similar elements. Exemplary embodiments will be explained in the following text with reference to the attached drawings, in which: [0008] FIGS. 1A-1C to FIGS. 5A-5C show simplified section views and plan views to illustrate fabrication of an interconnect arrangement according to a first exemplary embodiment; [0009] FIGS. 6A-6C to FIGS. 10A-10B show simplified section views and plan views to illustrate fabrication of an interconnect arrangement according to a second exemplary embodiment; and [0010] FIG. 11 shows a simplified plan view of an interconnect arrangement according to a third exemplary embodiment. [0011] Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. DETAILED DESCRIPTION [0012] An interconnect arrangement and method are disclosed in which a cavity is located at least underneath the interconnect and thus between the interconnect and the mount substrate. This makes it possible to reduce parasitic interconnect/substrate capacitances in semiconductor components such as semiconductor memory cells. The cavity may be bounded by a porous dielectric layer, which at the same time adheres to the interconnect and thus holds it, thus preventing the interconnect from falling or dropping down onto the mount substrate. Alternatively, this mounting option, which may be regarded as suspension of the interconnects, can also be provided by means of a supporting structure. In this case, the dielectric supporting elements, which support the interconnect from underneath, are formed in the cavity. [0013] The interconnect may have a contact via and/or a dummy contact via which lead/leads from the interconnect to the substrate surface and either makes or make electrical contact with or connects or connect to the substrate, or else touch or touches it and are or is not electrically connected to it. Contacts and/or additionally inserted dummy contacts which are present may be used as further supporting structures for the interconnect, thus reliably preventing the interconnect from falling down onto the mount substrate and a short-circuit being formed between the interconnect and the mount substrate. [0014] The interconnect may have a barrier layer to prevent interconnect material from diffusing into the mount substrate. In a similar way, a residual decomposition layer can also be formed in the cavity on the surface of the mount substrate, which can be used in the same way as the barrier layer and is produced, as a byproduct during removal of the sacrificial layer for the cavity. [0015] With regard to the production method, a sacrificial layer is formed on an electrically conductive mount substrate to provide suspension for the interconnects, an interconnect layer is formed on the sacrificial layer, and is structured together with the sacrificial layer. A porous dielectric layer is then formed over the entire surface, and the sacrificial layer is removed to form a cavity underneath the interconnect. This method makes it possible to also produce cavities underneath the interconnects. [0016] A polymer which is thermally stabilized up to about 300-400 degrees Celsius is applied as the sacrificial layer, with thermal conversion being carried out at temperatures from 300 to 600 degrees Celsius for removal of the sacrificial layer allowing the gaseous decomposition products created to escape through the porous layer. [0017] With regard to the alternative production method for provision of a support for interconnects, supporting structures are formed on a mount substrate, a sacrificial layer is then formed over the entire surface and is planarized as far as the surface of the supporting structure to form an interconnect layer on the planarized surface, and to structure it. Finally, the sacrificial layer is removed to form a cavity at least underneath the interconnect, and a closed dielectric covering layer is formed above the interconnects. In consequence, in this alternative, the interconnects are not mounted or suspended from above but are supported from underneath by means of a large number of supporting elements or pillars. The supporting elements may be arranged in straight lines or essentially at right angles to the interconnect, or may contain individual islands over which the interconnects pass. [0018] Turning to the figures, FIGS. 1A to 5C show simplified section views and plan views that illustrate method steps in the production of an interconnect arrangement according to a first exemplary embodiment. In this embodiment, the interconnects are held from above or at the sides by suspension. Each of the FIGS. C show plan views, with FIGS. A and B each showing the associated section views along a section A-A and B-B from the associated FIG. C. [0019] According to FIGS. 1A to 1C, a sacrificial layer 2 is formed on a mount substrate 1 which, for example, represents a semiconductor substrate. The semiconductor substrate can be formed from, for example, monocrystalline silicon. The sacrificial layer 2 may have openings 0 that extend as far as the mount substrate 1 to provide subsequent contacts. By way of example, a material which is thermally stable up to about 300-400 degrees Celsius (e.g. a polymer) may be applied as the sacrificial layer 2. Polyamides such as Parylene or Teflon may be used for this high-temperature-resistant polymer. These polyamides may be, for example, centrifuged on or deposited by CVD. Continue reading about Interconnect arrangement and associated production methods... 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