| Intelligent measurement modular semiconductor parametric test system -> Monitor Keywords |
|
|
  Intelligent measurement modular semiconductor parametric test systemUSPTO Application #: 20060212253Title: Intelligent measurement modular semiconductor parametric test system Abstract: An intelligent measurement modular semiconductor parametric test system comprises an engine control module. The engine control module is operable to communicate with a user via a user interface, and is further operable to communicate with and to control the state of at least one other module in the semiconductor parametric test system including pluggable modules. The engine control module is further operable to control test flow via a test monitor module based on data and control events received from an intelligent measurement module. Other modules in various embodiments comprise prober monitor modules. (end of abstract)
Agent: Schwegman, Lundberg, Woessner & Kluth, P.A. - Minneapolis, MN, US Inventors: Sergey A. Velichko, Michael J. Dorough, Robert G. Blunn USPTO Applicaton #: 20060212253 - Class: 702122000 (USPTO) Related Patent Categories: Data Processing: Measuring, Calibrating, Or Testing, Testing System, Including Specific Communication Means The Patent Description & Claims data below is from USPTO Patent Application 20060212253. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a Continuation of U.S. application Ser. No. 10/131,934, filed Apr. 25, 2002, which is incorporated herein by reference. [0002] The present invention is related to and claims priority from pending application Ser. No. 09/834,751, filed Apr. 13, 2001, titled "Concurrent control of semiconductor parametric testing". [0003] The present invention further claims priority from provisional application 60/293,280, filed May 23, 2001, titled "Concurrent and fault-tolerant control of semiconductor parametric testing". FIELD OF THE INVENTION [0004] The invention relates generally to testing semiconductors, and more specifically to fault-tolerant modular control of semiconductor parametric tests. BACKGROUND OF THE INVENTION [0005] Fabrication of semiconductors typically comprises many steps, including creation of a silicon wafer, deposition of various materials onto the wafer, ion implantation into the wafer, etching material applied to the wafer, and other similar processes. These processes are used to create the electronic components and connections on the wafer that form a useful electronic circuit. [0006] As these processes are performed on the wafer, the wafer may be subjected to parametric testing. Parametric testing involves testing the electronic parameters of the circuitry on the wafer, such as by applying current or voltage, and by measuring resistance, capacitance, current, voltage, or other such electrical parameters. These tests are used to ensure that a fabricated structure on the semiconductor meets the specifications and requirements of the semiconductor manufacturer and falls within acceptable tolerances. [0007] Parametric testing can take place during the fabrication process to ensure that each stage of fabrication is successful, and is usually performed on the completed wafer to ensure that each completed circuit on the wafer is functional and meets specified performance criteria. [0008] This parametric testing is typically performed with a parametric test system, which comprises several parts. Such systems may be capable of loading a wafer from a wafer tray to a wafer chuck, which is then positioned by a wafer positioner to a proper alignment under a test pin. Once the equipment has properly loaded and moved the wafer into position, parametric test instrumentation systems are initialized and operated to apply electrical signals, heat, and other stimuli as needed to the wafer. The test instrumentation also then takes measurements of parameters, such as impedance and current or voltage measurement, and the test system analyzes and records the results of the parametric tests. [0009] Although parametric testing is typically used to verify the parameters or performance of production semiconductors, such testing can also be critical in investigating the usability or performance characteristics of new materials or new circuit structures. A wide variety of tests, including resistance, capacitance, transistor characteristic, thermal characteristic, and other tests enable characterization of these new materials and circuits, as well as verification of performance in a production environment. [0010] Testing a single wafer can involve tens of thousands of measurements per wafer, with dozens of wafers per manufacturing lot or wafer tray loaded for test. Because this typically results in literally millions of parametric tests and measurements that must be performed per wafer lot, the complexity and speed of the parametric testing system is an important component in the efficient and profitable operation of a semiconductor fabrication facility. [0011] Fabrication facilities desiring to stay efficient and competitive therefore regularly change or upgrade the equipment they use, including probers, wafer loaders, and various measurement instrumentation systems. However, reconfiguration of a semiconductor parametric test system to incorporate new equipment is typically time consuming and expensive, requiring extensive reconfiguration of hardware and software. Highly customized semiconductor parametric test systems have therefore traditionally been prohibitively expensive to produce, given the limited life and upgradeability of such systems. [0012] It is therefore desirable to operate a semiconductor parametric test system that is both configurable and upgradable without extensive redesign of the entire semiconductor parametric test system. BRIEF DESCRIPTION OF THE FIGURES [0013] FIG. 1 shows an example configuration of a modular semiconductor parametric test system, consistent with an embodiment of the present invention. [0014] FIGS. 2A and 2B show a class diagram of a measurement collection including a measurement module in a semiconductor parametric test system, consistent with an embodiment of the present invention. [0015] FIG. 3 illustrates a composite state diagram of a test monitor module in a semiconductor parametric test system, consistent with an embodiment of the present invention. [0016] FIG. 4 illustrates a test monitor module use case diagram for a semiconductor parametric test system, consistent with an embodiment of the present invention. [0017] FIG. 5 illustrates a class diagram for an interface to a prober module, consistent with an embodiment of the present invention. DETAILED DESCRIPTION [0018] In the following detailed description of sample embodiments of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific sample embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical, electrical, and other changes may be made without departing from the spirit or scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the invention is defined only by the appended claims. [0019] The present invention provides a semiconductor parametric test system that is both configurable and upgradable without extensive redesign of the entire semiconductor parametric test system. This is accomplished in one embodiment of the invention via a modular semiconductor parametric test system having an engine control module. The engine control module of one embodiment provides a user interface such as through a personal computer console to facilitate control and monitoring. The engine control module is further operable in one embodiment to communicate with and to control the state of at least one other module in the semiconductor parametric test system, including pluggable modules. These other modules include test monitor modules, prober monitor modules, and measurement modules in various further embodiments of the invention. Continue reading... Full patent description for Intelligent measurement modular semiconductor parametric test system Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Intelligent measurement modular semiconductor parametric test system patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Intelligent measurement modular semiconductor parametric test system or other areas of interest. ### Previous Patent Application: Test apparatus and setting method therefor Next Patent Application: Automatic test equipment operating architecture Industry Class: Data processing: measuring, calibrating, or testing ### FreshPatents.com Support Thank you for viewing the Intelligent measurement modular semiconductor parametric test system patent info. IP-related news and info Results in 0.4871 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , |
||
