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  Integrated process for fuse opening and passivation process for cu/low-k imdUSPTO Application #: 20050218476Title: Integrated process for fuse opening and passivation process for cu/low-k imd Abstract: A new process flow is provided for the creation of a fuse contact and a bond pad. The invention starts with a semiconductor substrate over the surface of which is provided top level metal and fuse metal in the surface of a layer of insulation deposited over the surface of the substrate. A first etch stop layer is deposited over the surface of the layer of insulation over which a first passivation layer is deposited, an opening is created through these layers exposing the top level metal. A metal plug is created overlying the exposed surface of the top level metal. A stack of a patterned and etched hard mask layers, having been deposited at part of the creation of the metal plug and overlying a layer of metal plug material, remains in place over the surface of the created metal plug. A second layer of passivation material is deposited, the second layer of passivation is patterned and etched exposing the surface of the first layer of passivation overlying the fuse metal and exposing the surface of the stack of hard mask layers overlying the created metal plug. The stack of hard mask layers is then removed from the surface of the metal plug, exposing the surface of the metal plug to serve as a contact pad and further reducing the thickness of the first layer of passivation over the surface of the fuse metal, making the fuse more accessible for fuse blowing. (end of abstract) Agent: Haynes And Boone, LLP - Dallas, TX, US Inventors: Tze-Liang Lee, Chao-Chen Chen USPTO Applicaton #: 20050218476 - Class: 257529000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Integrated Circuit Structure With Electrically Isolated Components, Passive Components In Ics, Including Programmable Passive Component (e.g., Fuse) The Patent Description & Claims data below is from USPTO Patent Application 20050218476. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] (1) Field of the Invention [0002] The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for the creation of a reliable top metal fuse. [0003] (2) Description of the Prior Art [0004] Increased semiconductor device performance has over the years been achieved by decreasing device dimensions and by increasing device packaging densities. The therefrom following sharp reductions in device feature size imposes increasingly strict limitations on the technologies that are used for semiconductor device creation. Increasing device density requires the creation of more complex networks of interconnect traces over a surface in which multiple active semiconductor devices have previously been created, a requirement that is typically addressed by increasing the number of overlying layers of electrical interconnect wiring. It is in this respect not uncommon to use from two to six overlying layers of conductive interconnects, these layers of interconnects are embedded in layers of insulating material such as layers of Intra Level Dielectric (ILD) and Inter Metal Dielectric (IMD). After these layers of interconnect have been created, a passivation layer is generally deposited over the surface of the upper layer of insulation for the protection of the underlying semiconductor devices and the network of conductive interconnects. [0005] In addition to the above referred to active semiconductor devices that are provided over for instance the surface of a silicon substrate, semiconductor constructs frequently are also provided with means of further personalizing these devices by providing on or more fuses as part of the device. With the increased number of overlying layers of insulation and with the reduction in device feature size, the conventional approach of creating a poly fuse, that is accessed via an opening created through the layers of insulation, becomes less attractive and has therefore been replaced with the creation of metal fuses. Laser technology is typically and most beneficially used for the opening to the fuse for purposes of device personalization. These layers are, aligned with the fuse point of contact, penetrated, creating an opening through these layers that aligns with the fuse point of contact whereby however a fraction these layers remains in place over a height above the fuse point of contact. This layer overlying the fuse point of contact has as a design requirement that the layer remains a solid layer of consistent layer density, that is no cracks or other density disturbances are allowed in the fraction of the layer of insulation that remains in place overlying the fuse point of contact. The laser technology that is used for opening (or blowing) the fuse combined with the characteristics of the typically used low-K dielectrics that are used for the layers of insulation, readily and frequently lead to the occurrence of cracks in the remaining overlying layer of insulation, leading to increased product loss. [0006] An additional concern is the complexity of the process that is required in order to create the layers of interconnect traces in combination with electrical fuse capability. It is not uncommon to have a process requiring four steps of photoresist mask processing, each step in addition requiring relatively extensive steps of surface clean after the patterned layers of photoresist have been removed prior to additional processing steps. [0007] Concurrent with the creation of access to a fuse, openings are frequently created through the layers of insulation to a bond pad, which is a point of contact in the surface of the layers of insulating material. The non-exposed surface of the created bond pad remains covered with a layer of insulating material. Good adhesion is required in this interface between the bond pad and the partially overlying layer of insulating material for reasons of device performance of which most notably can be cited requirements of leakage currents from the bond pad to surrounding areas and contact resistance to the bond pad. [0008] The invention addresses these and other concerns by providing a sequence of processing steps for the creation of a fuse opening and a contact pad, also referred to as bond pad, through layers of passivation whereby negative effects that are typically experienced due to the presence of low-K dielectric overlying the fuse is eliminated. [0009] U.S. Pat. No. 6,162,686 (Huang et al.) shows a fuse opening process and passivation process. [0010] U.S. Pat. No. 5,985,765 (Hsiao et al.) shows integrated BP and fuse process. [0011] U.S. Pat. No. 6,235,557 B1 (Manley) shows a fuse, top metal and passivation process. [0012] U.S. Pat. No. 6,054,340 (Mitchell et al.) discloses another fuse and passivation process. SUMMARY OF THE INVENTION [0013] A principle objective of the invention is to provide a process flow for the creation of fuse access and a bond pad in which the number of photoresist and etching steps is reduced. [0014] Another objective of the invention is to provide a process for the creation of bond pad opening whereby bonding between the non-exposed surface of the bond pad and surrounding layers of insulating material is improved. [0015] Yet another objective of the invention is to improve overall semiconductor package reliability in creating fuse access and a bond pad at no additional manufacturing cost incurred by avoiding an increase in the required number of device exposures and the therewith associated use of exposure masks. [0016] In accordance with the objectives of the invention a new process flow is provided for the creation of a fuse contact and a bond pad. The invention starts with a semiconductor substrate over the surface of which semiconductor devices, components and conductive interconnects have been created, including top level metal and fuse metal in the surface of a layer of insulation deposited over the surface of the substrate. A first etch stop layer is deposited over the surface of the layer of insulation over which a first passivation layer is deposited, an opening is created through these layers exposing the top level metal. A metal plug is created overlying the exposed surface of the top level metal. A stack of a patterned and etched hard mask layers, having been deposited at part of the creation of the metal plug and overlying a layer of metal plug material, remains in place over the surface of the created metal plug. A second layer of passivation material is deposited over the surface of the structure, the second layer of passivation is patterned and etched exposing the surface of the first layer of passivation overlying the fuse metal and exposing the surface of the stack of hard mask layers overlying the created metal plug. The stack of hard mask layers is then removed from the surface of the metal plug, exposing the surface of the metal plug to serve as a contact pad and further reducing the thickness of the first layer of passivation over the surface of the fuse metal, making the fuse more accessible for fuse blowing. BRIEF DESCRIPTION OF THE DRAWINGS [0017] FIGS. 1 through 11 highlight conventional processing steps that are applied for the creation of a contact pad and the creation of an opening to a fuse point, as follows: [0018] FIG. 1 shows a cross section of a semiconductor surface such as the surface of a silicon substrate, a layer of interconnect metal has been created over the surface, a layer of top metal and a layer of metal fuse has been created in the surface of the layer of interconnect metal. [0019] FIG. 2 shows a cross section after deposition of a first layer of etch stop material and a first layer of passivation material. A first photoresist mask has been created. [0020] FIG. 3 shows a cross section after the etch of the first layer of passivation, the first photoresist mask has been removed. [0021] FIG. 4 shows a cross section after the first etch stop layer has been removed from above the pattern of top metal using the patterned and etch first layer of passivation as a mask. Continue reading... Full patent description for Integrated process for fuse opening and passivation process for cu/low-k imd Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Integrated process for fuse opening and passivation process for cu/low-k imd patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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