| Integrated lithography and etch for dual damascene structures -> Monitor Keywords |
|
|
 
Integrated lithography and etch for dual damascene structuresRelated Patent Categories: Radiation Imagery Chemistry: Process, Composition, Or Product Thereof, Imaging Affecting Physical Property Of Radiation Sensitive Material, Or Producing Nonplanar Or Printing Surface - Process, Composition, Or Product, Making Electrical DeviceIntegrated lithography and etch for dual damascene structures description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070166648, Integrated lithography and etch for dual damascene structures. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] The present invention generally relates to the manufacture of semiconductor devices and more particularly to an improved dual damascene process for creating dual damascene structures. [0002] Metal interconnections in very large scale integrated (VLSI) or ultra-large scale integrated (ULSI) circuits typically consist of interconnect structures containing patterned layers of metal wiring. Typical integrated circuit (IC) devices contain from three to fifteen layers of metal wiring. As feature sizes decrease and device density increases, the number of interconnect layers is expected to increase. [0003] Creation of the structure for metal lines for back end of line (BEOL) semiconductor manufacturing requires creating vias between two metal line levels. Usually, this entails two discrete lithographic and RIE operations to create the vias and trenches. In this invention we propose a process sequence which will enable integrated via and line lithography followed by integrated via and line etch. A novel two-layered, negative tone resist based lithography is used to generate a dual damascene structure in the photoresist which is subsequently transferred into the underlying interlayer dielectric (ILD) using an appropriate etch process. [0004] Creation of the structure for metal lines for BEOL semiconductor manufacturing requires creating metal line levels and via levels in a sequence such that the metal line levels are interconnected by via levels. Usually this entails two discrete lithographic and RIE operations to create the via and trench levels in separate steps. [0005] A typical dual damascene process sequence has several disadvantages. First a planarizing layer is required for the second patterning level. This planarization is not completely uniform and typically results in some topography which nay cause problems for the second lithography step. Second, it is a high cost process because it requires a special planarizing layer and requires multiple steps, two passes through the lithography tool and two passes through the RIE tool. This results in a longer process time and increased cost. Third, in applications using a low (<4.0) dielectric constant material in the BEOL, RIE damage to the dielectric material may result from the required strip of the planarizing layer. This is especially severe for porous ultra low dielectric constant materials. [0006] Other solutions have been proposed by others to solve these problems. U.S. Pat. No. 5,877,076 proposes using a combination of positive and negative resist in two separate patterning steps. However in this approach, additional time is required for the first photoresist layer. This development step could potentially create planarization issues. Additionally, this approach places the negative resist on top of the positive resist. Here, exposure of the negative resist in certain areas could cause the positive resist to dissolve and create adhesion problems and resist profile issues during etch in heavily patterned areas. Similarly, in U.S. Pat. No. 6,242,344, where a negative resist is placed on top of a positive resist before any patterning, the underlying positive photoresist will be exposed to some radiation and exhibit some level of film loss. This film loss could result in adhesion failure at the interface between resist layers. [0007] Therefore, a need exists for an improved dual damascene process. Accordingly, it is an object of the present invention to provide an integrated lithography step which does both via and line level patterning with two layers of negative resist in separate exposure steps. [0008] Another object of the present invention is to follow the lithography with an integrated RIE. These and other objects of the invention will become more apparent after referring to the following description of the invention. BRIEF SUMMARY OF THE INVENTION [0009] The present invention provides a process sequence which will enable integrated via and line lithography followed by integrated via and line etch. A novel two-layered, negative resist based lithography is used to generate a dual damascene structure in the photoresist which is subsequently transferred into the underlying ILD using an appropriate etch process. [0010] In a first embodiment of the present invention there is provided a method of dual damascene patterning through the use of a two-layered negative resist comprising the steps of providing a semiconductor substrate having an interlayer dielectric layer deposited thereon; forming a first negative resist layer on the interlayer dielectric layer; hole patterning the first negative resist layer by exposing and developing the first negative resist layer using a via level level mask; forming a second negative resist layer on the first negative resist layer; and line patterning the second negative resist layer by exposing and developing the second negative resist layer using a line level mask, thereby forming a via and line structure in the undeveloped resist. [0011] In another embodiment of the present invention there is provided a method of dual damascene patterning through the use of a two-layered negative resist comprising the steps of providing a semiconductor substrate having an interlayer dielectric layer deposited thereon; forming a first negative resist layer on the interlayer dielectric layer; exposing the first negative resist layer using a via level level mask; forming a second negative resist layer on the first negative resist layer; and hole and line patterning the first and second negative resist layers by exposing and developing the first and second negative resist layers using a line level mask, thereby forming a via and line structure in the undeveloped resist. The methods may further comprise a bake after exposing the first and second negative resists. [0012] In a preferred method of dual damascene patterning there is provided a two-layered negative resist and integrated RIE process comprising the steps of providing a semiconductor substrate having a cap layer thereon and an interlayer dielectric layer deposited on said cap layer; providing an etch stop layer on the interlayer dielectric layer and an organic layer on the etch stop layer; providing a hardmask layer on the organic layer; forming a first negative resist layer on the hardmask layer; hole patterning the first negative resist layer by exposing and developing the first negative resist layer using a via level level mask; forming a second negative resist layer on the first negative resist layer; and line patterning the second negative resist layer by exposing and developing the second negative resist layer using a line level mask, thereby forming a via and line structure in the undeveloped resist; and performing an oxide RIE to remove portions of the hardmask layer and transfer the via pattern into the surface of the organic layer. [0013] The preferred method further comprises the steps of etching the vias in the organic layer to the interlayer dielectric layer; forming the vias in the ILD layer to a depth such that they are at least below the final line depth but less than approximately 80% of said ILD layer thickness; removing the resist over the line using a strip process thereby etching away the hardmask over the line structure; etching the line pattern through the organic layer into the ILD layer; etching the ILD layer using an etch chemistry that is sufficiently selective to the organic layer; etching the vias down to the cap layer; removing the remaining organic layer; and opening the cap layer with a RIE process thereby connecting the vias to electrical structures in the substrate. [0014] The present invention also provides a method to correct via to line misalignment according to the disclosed method wherein the first negative resist layer is less sensitive than the second negative resist layer comprising the steps of providing the first negative resist with a thickness sufficient to be used for the entire etch process; providing the second negative resist with a thickness such that during the etch process the second negative resist fully consumed; and using a resist-only RIE process resulting in the transfer of the line structure into the first negative resist. [0015] The present invention also provides a dual damascene structure comprising a semiconductor substrate having an interlayer dielectric layer deposited thereon; a first negative resist layer on the interlayer dielectric layer, the first negative resist layer having developed first negative resist features therein; a second negative resist layer on the first negative resist layer, the second negative resist layer having developed second negative resist features therein; and the second developed negative resist features having an area greater than or equal to the area of the first developed negative resist features. [0016] The dual damascene structure may further comprise additional negative resist layers having developed negative resist features wherein each subsequent additional negative resist layer has developed negative resist features having an area greater or equal to the underlying developed negative resist features. BRIEF DESCRIPTION OF THE DRAWINGS [0017] The features of the invention believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The figures are for illustration purposes only and are not drawn to scale. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which: [0018] FIGS. 1-5 are schematic views of the two-layered, negative resist based lithography process used to generate a dual damascene structure. [0019] FIGS. 6-12 are schematic views of the integrated RIE process used to generate a two-layered, negative resist dual damascene structure. [0020] FIGS. 12-16 are schematic views of methods to correct misalignment in the integrated two-layered, negative resist dual damascene structure. DETAILED DESCRIPTION OF THE INVENTION Continue reading about Integrated lithography and etch for dual damascene structures... Full patent description for Integrated lithography and etch for dual damascene structures Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Integrated lithography and etch for dual damascene structures patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Integrated lithography and etch for dual damascene structures or other areas of interest. ### Previous Patent Application: Light sensitive planographic printing plate material and planographic printing plate manufacturing process Next Patent Application: Method of forming a micro device Industry Class: Radiation imagery chemistry: process, composition, or product thereof ### FreshPatents.com Support Thank you for viewing the Integrated lithography and etch for dual damascene structures patent info. IP-related news and info Results in 0.16695 seconds Other interesting Feshpatents.com categories: Electronics: Semiconductor , Audio , Illumination , Connectors , Crypto , 174 |
 * Protect your Inventions * US Patent Office filing 
PATENT INFO |
|
