| Integrated header switch with low-leakage pmos and high-leakage nmos transistors -> Monitor Keywords |
|
|
  Integrated header switch with low-leakage pmos and high-leakage nmos transistorsUSPTO Application #: 20070120578Title: Integrated header switch with low-leakage pmos and high-leakage nmos transistors Abstract: System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor's gate terminal is coupled to a separate control signal line. The PMOS transistor provides current to the circuits at high voltage supply levels while the NMOS transistor provides current to the circuits at low voltage supply levels, wherein the size of the PMOS and NMOS transistor can be changed during design to meet power requirements. Depending upon power requirements, multiple PMOS and NMOS transistors may be used. The combination of PMOS and NMOS transistors permit the use of limited fabrication processes wherein transistor widths can be limited. (end of abstract)
Agent: Texas Instruments Incorporated - Dallas, TX, US Inventors: Hugh T. Mair, David B. Scott, Rolf Lagerquist USPTO Applicaton #: 20070120578 - Class: 326083000 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20070120578. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This is a division of application Ser. No. 10/916,135, filed on Aug. 11, 2004. Benefit of the prior application is claimed. TECHNICAL FIELD [0002] The present invention relates generally to a system and method for providing power to integrated circuits, and more particularly to a system and method for providing power with a large on-current and a small off-current to circuitry in integrated circuits. BACKGROUND [0003] In order for logic circuitry in an integrated circuit to operate, it is necessary to provide power to the logic circuits. To power logic circuits, it may be necessary to provide a power supply connection and a ground connection. Furthermore, in order to minimize power consumption when the logic circuitry is inactive, it is desired that leakage current be minimized. Therefore, it is desired to have a large on-current to off-current ratio. [0004] Header and footer configurations are commonly used ways to provide the connections to the logic circuits, wherein a header configuration uses a switch to couple (and decouple) the logic circuits to a power supply and a footer configuration uses a switch to couple (and decouple) the logic circuits to a ground connection. Therefore, to provide power to the logic circuits, switches in both the header and the footer configurations could close, providing a current path from the power supply to the ground. For example, in a header configuration, typically PMOS (P-type Metal Oxide Semiconductor) transistors can be used as a switch to cut the power supply connection to the logic circuits, while in a footer configuration, typically NMOS (N-type Metal Oxide Semiconductor) transistors can be used to cut the ground connection to the logic circuits. [0005] Variations in the header and footer configurations have included the use of high threshold voltage and low threshold voltage PMOS and NMOS transistors to help improve the on-current to off-current ratio. In some variations, even NMOS transistors have been used as switches in header configurations. In certain manufacturing processes, wherein it may be possible to create transistors with wide variations in geometries (and other parameters), the use of the header and footer configurations can provide both a large on-current and small off-current. [0006] One disadvantage of the prior art is that in many manufacturing processes wherein the ability to vary the widths of transistors is limited, it may be difficult to use standard transistors in the header and footer configurations and still provide both a large on-current and a small off-current. [0007] One disadvantage of the prior art is that in many manufacturing processes wherein the ability to vary the widths of transistors is limited, it may be difficult to use standard transistors in the header and footer configurations and still provide both a large on-current and a small off-current. [0008] A second disadvantage of the prior art is that the use of high and low threshold voltage transistors may preclude the use of a manufacturing process wherein a limited number of transistor sizes may be used. The use of transistors with limited sizes can reduce the ability to provide a satisfactory on-current to off-current ratio. SUMMARY OF THE INVENTION [0009] These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention which provides for a system and method for providing power with a large on-current and a small off-current to circuitry in integrated circuits. [0010] In accordance with a preferred embodiment of the present invention, a combination header switch for use in providing power to circuitry in an integrated circuit, wherein the combination header switch comprises a PMOS (P-type Metal Oxide Semiconductor) transistor having a gate terminal coupled to a first control signal line, an NMOS (N-type Metal Oxide Semiconductor) transistor having a gate terminal coupled to a second control signal line, and wherein each transistor's first terminals are coupled to a voltage supply and each transistor's second terminals are coupled to an output of the combination header switch, and wherein the size of the PMOS and NMOS transistors are adjusted to provide required current levels to the circuitry as a function of voltage supply level is provided. [0011] In accordance with another preferred embodiment of the present invention, an integrated circuit comprising a logic circuit and a combination header switch coupled between a voltage supply and the logic circuit, the combination header switch configured to provide current to the logic circuit as a function of the level of the voltage supply, wherein the combination header switch comprises a PMOS (P-type Metal Oxide Semiconductor) transistor having a gate terminal coupled to a first control signal line, an NMOS (N-type Metal Oxide Semiconductor) transistor having a gate terminal coupled to a second control signal line, and wherein the NMOS transistor comprises a plurality of NMOS transistors coupled in parallel and the PMOS transistor comprises a plurality of PMOS transistors coupled in parallel is provided. [0012] In accordance with yet another preferred embodiment of the present invention, a method for designing an integrated circuit, the method comprising specifying frequency targets for the logic gates within the integrated circuit, determining currents to the logic gates based on the frequency targets, and then sizing a combination header switch so that the combination header switch can provide the determined currents is provided. [0013] An advantage of a preferred embodiment of the present invention is that a header switch with a large on-current to off-current ratio can be created using a manufacturing process wherein the manufacturing process is not capable of fabricating transistors with a wide range of sizes (and perhaps other parameters). This can enable the use of these limited fabrication processes, possibly resulting in a lower unit cost for the integrated circuits since a design with fewer transistor types can be used. [0014] A further advantage of a preferred embodiment of the present invention is that the design of the header switch can be readily adapted to meet different current needs of different integrated circuits. Therefore, the header switch can be modified for each integrated circuit design's needs, thereby offering optimized performance. Additionally, since the header switch can be modified for an integrated circuit's needs, there is no need to used a header switch with more capability than required. This can minimize cost by reducing unneeded hardware. [0015] The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0016] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which: [0017] FIG. 1 is a diagram of a schematic of a header configuration used to provide a voltage supply to a circuit; [0018] FIG. 2 is a digram of a schematic of a footer configuration used to provide an electrical ground to a circuit; [0019] FIGS. 3a through 3c are diagrams of schematics of prior art implementations of header and footer configurations used to provide power to a circuit while maintaining a high on-current to off-current ratio; [0020] FIG. 4 is a diagram of a high-level view of a schematic of a header configuration used to provide a voltage supply to a logic circuit, wherein a combination switch is used to provide a high on-current to off-current ratio, according to a preferred embodiment of the present invention; Continue reading... Full patent description for Integrated header switch with low-leakage pmos and high-leakage nmos transistors Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Integrated header switch with low-leakage pmos and high-leakage nmos transistors patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Integrated header switch with low-leakage pmos and high-leakage nmos transistors or other areas of interest. ### Previous Patent Application: Semiconductor integrated apparatus using two or more types of power supplies Next Patent Application: Integrated circuit device and electronic instrument Industry Class: Electronic digital logic circuitry ### FreshPatents.com Support Thank you for viewing the Integrated header switch with low-leakage pmos and high-leakage nmos transistors patent info. IP-related news and info Results in 0.74757 seconds Other interesting Feshpatents.com categories: Accenture , Agouron Pharmaceuticals , Amgen , AT&T , Bausch & Lomb , Callaway Golf |
||
