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Integrated circuits with contemporaneously formed array electrodes and logic interconnectsRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Contacting Multiple Semiconductive Regions (i.e., Interconnects)Integrated circuits with contemporaneously formed array electrodes and logic interconnects description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060099797, Integrated circuits with contemporaneously formed array electrodes and logic interconnects. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a divisional application of U.S. application Ser. No. 10/369,277, filed Feb. 18, 2003, the entirety of which is incorporated by reference herein. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention generally relates to methods and apparatus for metallization in data storage devices for integrated circuits, and more particularly, to randomly accessible memory devices. [0004] 2. Description of the Related Art [0005] Computers and other digital systems use memory to store programs and data. A common form of memory is random access memory (RAM). Many memory devices, such as dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices are volatile memories. A volatile memory loses its data when power is removed. For example, after a conventional personal computer is powered off, the volatile memory is typically reloaded through a boot up process upon a restart. In addition, certain volatile memories such as DRAM devices require periodic refresh cycles to retain data even when power is continuously supplied. [0006] Nonvolatile memory devices retain data for long periods of time when power is removed. Examples of nonvolatile memory devices include read only memory (ROM), programmable read only memory (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, and the like. These memory devices are also randomly addressable memory devices. Disadvantageously, conventional nonvolatile memories are relatively large (physically), slow, and expensive. Further, conventional nonvolatile memories are relatively limited in write cycle capability and typically can only be programmed to store data about 10,000 times in a particular memory location. This prevents a conventional non-volatile memory device, such as a flash memory device, from being used as general purpose memory. [0007] An alternative memory device is known as magnetoresistive random access memory (MRAM). An MRAM device uses magnetic orientations to retain data in its memory cells. Advantageously, MRAM devices are relatively fast, are nonvolatile, consume relatively little power, and do not suffer from restrictive write cycle limitations. There are many different types of MRAM devices. [0008] In a giant magneto-resistance (GMR) MRAM cell, at least two ferromagnetic layers are separated by a non-magnetic layer. One of the ferromagnetic layers has a relatively high coercivity and is provided a fixed or "pinned" magnetic vector. The other ferromagnetic layer has a lower coercivity, wherein the orientation of its magnetic vector can be "varied" by a field not large enough to re-orient the pinned layer. [0009] In a tunneling magneto-resistance (TMR) cell, the layer of non-magnetic material corresponds to a relatively thin layer of insulating material, which is made thin enough to permit electron tunneling, i.e., quantum mechanical tunneling of electrons from one of the ferromagnetic layers to the other. The passage of electrons through the stack of layered materials depends upon the orientation of the magnetic vector of the soft magnetic or variable layer relative to that of the pinned layer; electrons pass more freely when the magnetic vectors of the variable and pinned layers are aligned. [0010] The demand for larger and larger memory devices is ever increasing. To meet the demand for larger memory, even more memory cells are packed into memory arrays of memory devices. This increases the number of electrodes for memory cells and interconnects for logic throughout the memory device. Electrodes and interconnects are typically fabricated by forming layers of interlayer dielectric (ILD) and layers of metallization. The fabrication of multiple layers of metallization can be time consuming and expensive. SUMMARY OF THE INVENTION [0011] Embodiments of the invention include a fabrication process and an apparatus for providing interconnects in a memory device. Advantageously, embodiments of the invention contemporaneously form electrodes for memory arrays and interconnects for logic circuits at the same time. This advantageously saves processing steps and time as compared to forming electrodes and forming interconnects in separate steps. With fewer processing steps, integrated circuits can be formed in less time and with fewer sources of error. [0012] One embodiment of the invention is an integrated circuit memory device. The integrated circuit device has a semiconductor substrate assembly. Memory cells, such as MRAM memory cells, are arranged in a memory array above the substrate assembly. A plurality of metallization layers form electrodes for the memory array. At least one of these metallization layers is also configured to form interconnects for logic circuits. In one embodiment, an optional cladding of a magnetic material, such as nickel-iron, forms a magnetic keeper for the electrodes. In one embodiment, the electrodes for the memory array and the interconnects for the logic circuits have unequal pitches. This can advantageously reduce electromigration, reduce distributed capacitance, etc. [0013] Another embodiment of the invention is a method of forming electrodes and interconnects for an integrated circuit memory device. A metallization layer is formed. Electrodes for a memory array and interconnects for logic are simultaneously formed from the metallization layer. This advantageously saves processes steps, thereby speeding up manufacturing processes and decreasing the number of process steps to fabricate electrodes and/or interconnects. BRIEF DESCRIPTION OF THE DRAWINGS [0014] These and other features of the invention will now be described with reference to the drawings summarized below. These drawings (not to scale) and the associated description are provided to illustrate preferred embodiments of the invention and are not intended to limit the scope of the invention. [0015] FIG. 1 illustrates a randomly accessible memory device. [0016] FIG. 2 is a schematic top view of a substrate assembly of an integrated circuit memory device. [0017] FIG. 3 illustrates a cross-sectional view of an integrated circuit memory device illustrating contemporaneously fabricated electrodes for the memory array and interconnects for logic. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS [0018] Although this invention will be described in terms of certain preferred embodiments, other embodiments that are apparent to those of ordinary skill in the art, including embodiments that do not provide all of the benefits and features set forth herein, are also within the scope of this invention. Accordingly, the scope of the invention is defined only by reference to the appended claims. [0019] The invention relates to metallization for an integrated circuit, including an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for memory devices in relatively few steps. Embodiments of the invention also include memory devices with metallization layers having unequal pitch dimensions in different areas of the chip, thereby permitting simultaneous fabrication of array electrodes and logic interconnects in different areas of the chip. This reduces the number of fabrication steps used to make interconnects, thereby reducing sources of error, speeding up fabrication, and reducing production costs. Continue reading about Integrated circuits with contemporaneously formed array electrodes and logic interconnects... Full patent description for Integrated circuits with contemporaneously formed array electrodes and logic interconnects Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Integrated circuits with contemporaneously formed array electrodes and logic interconnects patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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