| Integrated circuit routing resource optimization algorithm for random port ordering -> Monitor Keywords |
|
|
  Integrated circuit routing resource optimization algorithm for random port orderingUSPTO Application #: 20050262464Title: Integrated circuit routing resource optimization algorithm for random port ordering Abstract: A method of routing an integrated circuit signal bus is provided. One of a set of blocks having ports that are to be connected to the signal bus is selected as a primary block, the ports of which are positioned so that no two ports of that block lie within the same routing track parallel to the closest portion of a primary bus route. All other blocks, termed secondary blocks, have ports that are positioned so that no two ports of any secondary block reside within the same routing track perpendicular to the closest portion of the primary bus route. A primary connection for each signal of the signal bus is then placed over each port of the primary block substantially along the length of the primary route. Each port of each secondary block then has a secondary track connecting it in a perpendicular fashion to the proper primary track. (end of abstract) Agent: Agilent Technologies, Inc. Legal Department, Dl429 - Loveland, CO, US Inventors: Gerald L. Esch, Richard S. Rodgers USPTO Applicaton #: 20050262464 - Class: 716012000 (USPTO) Related Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Routing (e.g., Routing Map, Netlisting) The Patent Description & Claims data below is from USPTO Patent Application 20050262464. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] As integrated circuit (IC) technology continues to evolve, the use within ICs of wide multi-signal buses, such as data buses, becomes more prevalent. Generally speaking, such buses consume large amounts of limited routing resources, causing routing problems for both the bus and other signal connections within an IC. Also, as the functional capacity of ICs increase, the interconnections required between circuit "blocks" of the IC increase as well, thus exacerbating the routing problem. [0002] FIG. 1 exemplifies this problem by way of a simplified diagram. Three circuit blocks 2a, 2b and 2c are each connected to a signal bus comprised of signals 0 through n. Each block thus contains n+1 separate ports P, each of which is to be connected to the corresponding signal of the signal bus. Unfortunately, as is often the case, the ports P of each block 2 do not align with each other, but are instead ordered somewhat randomly within each block 2. As a result, each signal connection 1 requires the use of several vertical and horizontal routing resources, called "tracks," to implement the necessary connections. As more vertical and horizontal tracks are used, more routing resources are consumed, resulting in fewer routing options for other IC signals. In many cases, routing of such buses often causes enough congestion within the tracks to make routing of the entire IC problematic. [0003] To help alleviate such routing congestion, IC designers sometimes force the placement of the ports within each block in an orderly fashion. An example of this port placement is shown in FIG. 2. Blocks 3a, 3b and 3c each employ ports P which are placed in order from signal 0 through signal n. As a result, each signal connection 1 requires the use of a single vertical routing track and no horizontal routing tracks, thus consuming substantially fewer routing resources than what were required with the random port ordering of FIG. 1. [0004] However, such orderly port placement within each block often creates a burden on the IC designer in terms of time and effort to architect each block to minimize routing resources. Additionally, many block designs simply preclude such orderly port alignment. [0005] From the foregoing, a need exists for the ability to optimize the routing of IC inter-block signals among blocks utilizing somewhat randomly placed ports. Such ability would reduce the substantial amount of routing resources typically required for signal buses while eliminating the burden of orderly port placement on the IC designer. SUMMARY OF THE INVENTION [0006] Embodiments of the invention, to be discussed in detail below, provide a method for routing an IC signal bus efficiently while minimizing the routing resources consumed. One of a set of blocks to be connected to the bus is selected as a primary block, the ports of which are to be positioned so that no two ports of the primary block reside within the same routing track running parallel to a primary bus route. All other blocks, known as secondary blocks, have ports positioned so that no two ports of each separate block reside within the same routing track running perpendicular to the primary bus route. A primary connection for each signal of the bus is then aligned over each primary block port, extending essentially along the length of the primary bus route. Each secondary block port then has a secondary connection associated with it that connects that port to the primary connection associated with that port in a perpendicular manner. [0007] Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [0008] FIG. 1 is a diagram of an IC bus signal connection scheme from the prior art. [0009] FIG. 2 is a diagram of an IC bus signal connection scheme from the prior art, wherein the block port placements of each block are forced to coincide. [0010] FIG. 3 is a diagram of an IC bus signal connection scheme according to an embodiment of the invention, wherein the circuit blocks and primary bus route are aligned vertically. [0011] FIG. 4 is a diagram of an IC bus signal connection scheme according to an embodiment of the invention, wherein the circuit blocks and primary bus route are aligned horizontally. [0012] FIG. 5 is a diagram of an IC bus signal connection scheme according to an embodiment of the invention, wherein the circuit blocks are aligned so that the primary bus route runs both vertically and horizontally. [0013] FIG. 6 is a flow diagram of a method for routing an IC signal bus according to an embodiment of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0014] A simplified embodiment of the invention is shown in FIG. 3, using the method 100 for routing an IC signal bus, as shown in FIG. 6. Three circuit blocks 12a, 12b and 12c of an IC are aligned vertically. Ports P, numbered 0 through n, of each block are to be connected by way of a signal bus. In order to promote efficient utilization of the routing resources of the IC while allowing a measure of design freedom in the location of the ports P of each block 12, one of the circuit blocks 12 is selected as a primary block (step 110 of FIG. 6). In the specific example of FIG. 3, circuit block 12a is designated as the primary block, with the remaining blocks 12b and 12c thus being defined as secondary blocks. [0015] The ports of the primary block are then positioned so that no two of those ports reside in the same routing track running parallel to a primary bus route (step 120 of FIG. 6). With respect to FIG. 3, the primary block 12a has ports P aligned along the bottom edge of the block. This alignment allows a primary bus route which runs substantially vertically over each of the blocks 12. Thus, the port alignment of the primary block 12a ensures that the bus connection to each of these ports P will occupy a separate vertical routing track within that primary bus route. In alternate embodiments, as applied to different block configurations, the primary bus route may run near some of the blocks without actually passing directly over them. [0016] In alternate embodiments, the ports of the primary block will not strictly form a straight line; each port of the primary block need only reside within a separate routing track parallel to the primary bus route. However, in the case of FIG. 3, is horizontal alignment of the ports P along the edge of the primary block 12a nearest the secondary blocks 12b and 12c retains the advantages of maintaining the shortest routing path among the circuit blocks 12, as well as freeing up additional vertical routing resources over the remainder of the primary block 12a for other circuit connections. [0017] Ports for each of the secondary blocks are then positioned so that no two ports within a single secondary block reside in a single routing track perpendicular to the primary bus route (step 130 of FIG. 6). As shown in FIG. 3, the secondary blocks 12b and 12c each have ports P aligned along one of the vertical edges of the block. Such an alignment allows the connection of each port P to the signal bus by way of a distinct horizontal routing track. In other possible embodiments, the ports of each secondary block will not necessarily form a straight line; all that is needed is for each port of each secondary block to reside in a separate routing track perpendicular to the primary bus route. [0018] Once the ports are positioned, a primary connection is placed over each port of the primary block substantially along the length of and parallel to the primary bus route (step 140 of FIG. 6). Referring to FIG. 3, a set of primary connections 10 provides connection to the ports P of the primary block 12a. In this case, the primary connections 10 lie within distinct vertical routing tracks, one for each port P of the primary block 12a. [0019] Also, a secondary connection is placed to connect each port of each secondary block with the appropriate primary connection in a perpendicular manner (step 150 of FIG. 6). In the particular case of FIG. 3, the secondary connections 11 of the secondary blocks 12b and 12c connect the ports P of those blocks with the primary connections 10. The secondary connections 11 extend horizontally in this example, being substantially perpendicular to the vertical connections 10. [0020] Generally speaking, horizontal routing tracks reside on a separate IC layer from vertical routing tracks in order to efficiently utilize all IC resources dedicated to is routing of signals. As a result, the connections between horizontal and vertical routing tracks, as well as between routing tracks and the ports of the circuit blocks, are implemented by interlayer connections. A positive consequence of such an arrangement is that horizontal tracks cross over or under vertical tracks without unintended connection between the two. For example, referring to FIG. 3, the secondary connection 11 for Port 1 of the secondary block 12b, while being connected with the primary connection 10 for Port 1 of the primary block 12a, passes across all of the remaining primary connections 10 associated with the signal bus without making an electrical connection with them. Continue reading... Full patent description for Integrated circuit routing resource optimization algorithm for random port ordering Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Integrated circuit routing resource optimization algorithm for random port ordering patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Integrated circuit routing resource optimization algorithm for random port ordering or other areas of interest. ### Previous Patent Application: Wiring optimizations for power Next Patent Application: Handling of unused coreware with embedded boundary scan chains to avoid the need of a boundary scan synthesis tool during custom instance creation Industry Class: Data processing: design and analysis of circuit or semiconductor mask ### FreshPatents.com Support Thank you for viewing the Integrated circuit routing resource optimization algorithm for random port ordering patent info. IP-related news and info Results in 3.96547 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , |
||
