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Integrated circuit for receiving dataRelated Patent Categories: Electrical Computers And Digital Processing Systems: Memory, Storage Accessing And ControlIntegrated circuit for receiving data description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070180185, Integrated circuit for receiving data. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority under 35 U.S.C. .sctn.119 to Application No. DE 102006004229.8 filed on Jan. 30, 2006, entitled "Integrated Circuit for Receiving Data," the entire contents of which are hereby incorporated by reference. BACKGROUND [0002] An integrated semiconductor memory, for example a DRAM (Dynamic Random Access Memory) semiconductor memory, generally includes control connections for applying control signals, address connections for applying address signals, and data connections for applying data. In the event of a write access operation, a write command is applied to the control connections and an address signal is applied to the address connections. This makes it possible to activate at least one memory cell in a memory cell array of the integrated semiconductor memory for a write access operation. [0003] The data to be stored is applied to the data connections which are connected to receiving circuits in the semiconductor memory. The characteristic variables of the specification for a receiving circuit for receiving data include the set-up times and hold times. The latter are used to specify the time for which a data item must be applied at least to one of the data connections in order to be able to read the data item into the semiconductor memory in a clear and reliable manner. As a result of the increase in the access speed and thus in the operating frequency during the development of semiconductor memories in recent years, the time window in which valid data is applied to the semiconductor memory has become increasingly small. The receiving circuits must therefore accept the data into the semiconductor memory from the data connections within a very small time window. [0004] FIG. 1 shows an integrated circuit ES' of a semiconductor memory, in which a differential amplifier D is connected to an input connection E1 for applying a reference signal VREF and to an input connection E2 for applying a data signal (e.g., an input signal) DQ. The differential amplifier D compares a level of the data signal DQ with a level of the reference signal VREF and generates, at the output, an output signal which has a high or low level, is amplified by downstream amplifiers V1 and V2 and is forwarded to an output connection A. From there, the amplified data signals are generally supplied, via read/write amplifiers, to a memory cell array of an integrated semiconductor memory. [0005] As shown in FIG. 1, input signals for the integrated semiconductor memory, for example the data signals DQ, are received using a differential amplifier. The problem with this is, in particular, that the differential amplifier is not driven by differential input signals but rather by an input signal level and a constant reference signal level. In this case, different delays generally arise when receiving a rising or falling edge of the input signal. This consequently produces, at the output connection A, an output signal whose duty cycle is distorted with respect to the input signal. If, for example, the differential amplifier is supplied with an input signal which, during a clock period, has a high level for half of the period duration and a low level for the other half of the period duration, an output signal in which the high and low levels have different durations is produced at the output connection A. SUMMARY [0006] The described device relates to an integrated circuit for receiving data. The integrated circuit includes an input receiver circuit that is supplied with a data signal and a reference signal. The input receiver circuit converts the data signal into differential input control signals that are supplied to first and second signal paths. The first and second signal paths being connected in parallel. The first signal path includes a first comparator circuit that is connected, via a delay circuit and an amplifier circuit, to an output connection of the integrated circuit. The second signal path includes a second comparator circuit that is likewise connected, via a first inverter circuit and a second inverter circuit, to the output connection of the integrated circuit. The two amplifier circuits act as edge discriminators that drive each other and make it possible to generate, at the output connection, an output signal with the same duty cycle as the data signal without distortion. [0007] The above and still further features and advantages of the integrated circuit will become apparent upon consideration of the following definitions, descriptions and descriptive figures of specific embodiments thereof, wherein like reference numerals in the various figures are utilized to designate like components. While these descriptions go into specific details of the invention, it should be understood that variations may and do exist and would be apparent to those skilled in the art based on the descriptions herein. BRIEF DESCRIPTION OF THE DRAWINGS [0008] The integrated circuit is explained in more detail below with reference to exemplary embodiments, where: [0009] FIG. 1 shows a known integrated circuit for receiving data; [0010] FIG. 2 shows a first embodiment of the integrated circuit for receiving data; [0011] FIG. 3 shows a signal state diagram of signals in the integrated circuit shown in FIG. 2; [0012] FIG. 4 shows a second embodiment of the integrated circuit for receiving data; [0013] FIG. 5 shows a third embodiment of the integrated circuit for receiving data; [0014] FIG. 6 shows a first embodiment of the integrated circuit for receiving data and for generating complementary output signals; [0015] FIG. 7 shows a second embodiment of the integrated circuit for receiving data and for generating complementary output signals; [0016] FIG. 8 shows an embodiment of an inverter circuit of the integrated circuit for receiving data; and [0017] FIG. 9 shows an integrated semiconductor memory including the integrated circuit for receiving data. DETAILED DESCRIPTION [0018] The integrated circuit described herein converts an input signal into an output signal with as little distortion as possible. The integrated circuit includes a first input connection for applying a reference signal and a second input connection for applying an input signal and an output connection for generating an output signal. The integrated circuit further comprises an input receiver circuit for receiving the input signal and the reference signal and for generating first and second input control signals. In this case, the input receiver circuit is configured such that a respective level of the first and second input control signals is generated on the basis of a respective level of the input signal and of the reference signal, and also generates a level profile of the first input control signal that is complementary to a level profile of the second input control signal. In addition, the integrated circuit includes a first comparator circuit with an input side for receiving the first and second input control signals and an output side for generating a first comparison signal, the first comparator circuit being configured such that it generates the first comparison signal on the basis of a level of the first and second input control signals. The integrated semiconductor memory also includes a second comparator circuit with an input side for receiving the first and second input control signals and an output side for generating a second comparison signal, the second comparator circuit being configured such that it generates the second comparison signal on the basis of the level of the first and second input control signals. The integrated circuit further comprises an inverter circuit whose input is supplied with the second comparison signal for generating an inverted second comparison signal. The integrated circuit also includes a delay circuit whose input is supplied with the first comparison signal for generating a first comparison signal which is delayed with respect to the first comparison signal. The integrated circuit further comprises a first amplifier circuit for amplifying the delayed first comparison signal and generating a first output signal, the first output signal being amplified in comparison to the delayed first comparison signal. In addition, the integrated circuit includes a second amplifier circuit for amplifying the inverted second comparison signal and generating a second output signal. The output connections of the first and second amplifier circuits are connected to the output connection of the integrated circuit. [0019] One embodiment of the integrated circuit comprises an activation circuit for activating/deactivating the delay circuit includes an input connection for applying an activation signal. The activation circuit is designed in such a manner that it generates, at the output, a first control signal for activating/deactivating the delay circuit on the basis of a state of the activation signal. Continue reading about Integrated circuit for receiving data... Full patent description for Integrated circuit for receiving data Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Integrated circuit for receiving data patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Integrated circuit for receiving data or other areas of interest. ### Previous Patent Application: Hologram retrieval method and holographic recording and reproducing apparatus Next Patent Application: Semiconductor device and control method therefor Industry Class: Electrical computers and digital processing systems: memory ### FreshPatents.com Support Thank you for viewing the Integrated circuit for receiving data patent info. IP-related news and info Results in 0.18583 seconds Other interesting Feshpatents.com categories: Accenture , Agouron Pharmaceuticals , Amgen , AT&T , Bausch & Lomb , Callaway Golf 174 |
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