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Integrated circuit die/package interconnectRelated Patent Categories: Semiconductor Device Manufacturing: Process, Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor, Incorporating Resilient Component (e.g., Spring, Etc.)Integrated circuit die/package interconnect description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20080096323, Integrated circuit die/package interconnect. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND [0001] An integrated circuit (IC) die may include electrical devices that are integrated with a semiconductor substrate. The IC die may also include conductive paths that electrically couple the electrical devices to one another and to external connections. The die may include several layers of conductive paths, with each layer separated from adjacent layers by an inter-layer dielectric (ILD). The ILD may comprise a material having an extremely low dielectric constant (k) in order to minimize capacitance coupling and crosstalk between the conductive paths. [0002] Low-k ILD materials often exhibit a coefficient of thermal expansion (CTE) that differs significantly from other elements to which they are coupled, such as the other elements of an IC die and an IC package. Moreover, these materials are often brittle. Many low-k ILD materials are prone to cracking during IC die fabrication and/or operation due to these characteristics. BRIEF DESCRIPTION OF THE DRAWINGS [0003] FIG. 1 is a cutaway side view of an apparatus according to some embodiments. [0004] FIG. 2A is a top view and FIG. 2B is a bottom view of an apparatus according to some embodiments. [0005] FIG. 3 is a cutaway side view of an IC substrate, an IC die, and an apparatus according to some embodiments. [0006] FIG. 4 is a diagram of a process to fabricate the FIG. 3 device according to some embodiments. [0007] FIG. 5 is a side view of an integral conductive element according to some embodiments. [0008] FIG. 6 is a side view of an integral conductive element in combination with pliant material according to some embodiments. [0009] FIG. 7 is a side view of an integral conductive element, pliant material, and a carrier according to some embodiments. [0010] FIG. 8 is a side view of an integral conductive element, pliant material, a carrier, and photoresist according to some embodiments. [0011] FIG. 9 is a side view of an integral conductive element, pliant material, a carrier, and photoresist according to some embodiments. [0012] FIG. 10 is a side view of a plurality of pliant conductive elements, pliant material, and a carrier according to some embodiments. [0013] FIG. 11 is a cutaway side view of a plurality of pliant conductive elements, pliant material, second pliant material, and a carrier according to some embodiments. [0014] FIG. 12 is a cutaway side view of an apparatus according to some embodiments. [0015] FIG. 13 is a diagram of a process to fabricate the FIG. 3 device according to some embodiments. [0016] FIG. 14 is a side view of a carrier and pliant elements according to some embodiments. [0017] FIG. 15 is a side view of a carrier and pliant elements according to some embodiments. [0018] FIG. 16 is a side view of an integral conductive element, pliant elements, and a carrier according to some embodiments. [0019] FIG. 17 is a side view of an integral conductive element, pliant elements, a carrier, and photoresist according to some embodiments. [0020] FIG. 18 is a side view of an integral conductive element, pliant elements, a carrier, and photoresist according to some embodiments. [0021] FIG. 19 is a side view of a plurality of pliant conductive elements, pliant elements, and a carrier according to some embodiments. [0022] FIG. 20 is a cutaway side view of a plurality of pliant conductive elements, pliant elements, second pliant material, and a carrier according to some embodiments. Continue reading about Integrated circuit die/package interconnect... Full patent description for Integrated circuit die/package interconnect Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Integrated circuit die/package interconnect patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Integrated circuit die/package interconnect or other areas of interest. ### Previous Patent Application: Manufacturing method of semiconductor chip Next Patent Application: Chip packaging process Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Integrated circuit die/package interconnect patent info. IP-related news and info Results in 0.12245 seconds Other interesting Feshpatents.com categories: Electronics: Semiconductor , Audio , Illumination , Connectors , Crypto , 174 |
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