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Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubesRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Contacting Multiple Semiconductive Regions (i.e., Interconnects), Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization)Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070184647, Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATION [0001] This is a divisional application of U.S. patent application Ser. No. 11/008,800, filed Dec. 9, 2004, entitled "INTEGRATED CIRCUIT CHIP UTILIZING DIELECTRIC LAYER HAVING ORIENTED CYLINDRICAL VOIDS FORMED FROM CARBON NANOTUBES", which is herein incorporated by reference. FIELD OF THE INVENTION [0002] The present invention relates to digital data processing, and in particular to the design of integrated circuit chips used as components of digital data systems. BACKGROUND OF THE INVENTION [0003] In the latter half of the twentieth century, there began a phenomenon known as the information revolution. While the information revolution is a historical development broader in scope than any one event or machine, no single device has come to represent the information revolution more than the digital electronic computer. The development of computer systems has surely been a revolution. Each year, computer systems become faster, store more data, and provide more applications to their users. [0004] A modern computer system typically comprises a central processing unit (CPU) and supporting hardware necessary to store, retrieve and transfer information, such as communications buses and memory. It also includes hardware necessary to communicate with the outside world, such as input/output controllers or storage controllers, and devices attached thereto such as keyboards, monitors, tape drives, disk drives, communication lines coupled to a network, etc. The CPU is the heart of the system. It executes the instructions which comprise a computer program and directs the operation of the other system components. [0005] From the standpoint of the computer's hardware, most systems operate in fundamentally the same manner. Processors are capable of performing a limited set of very simple operations, such as arithmetic, logical comparisons, and movement of data from one location to another. But each operation is performed very quickly. Programs which direct a computer to perform massive numbers of these simple operations give the illusion that the computer is doing something sophisticated. What is perceived by the user as a new or improved capability of a computer system is made possible by performing essentially the same set of very simple operations, but doing it much faster. Therefore continuing improvements to computer systems require that these systems be made ever faster. [0006] The overall speed of a computer system (also called the throughput) may be crudely measured as the number of operations performed per unit of time. There are numerous ways in which system speed might be improved, but conceptually the simplest and most fundamental of all improvements is to increase the speed at which the basic circuits operate, i.e., to increase the clock speeds of the various components, and particularly the clock speed of the processor(s). E.g., if everything runs twice as fast but otherwise works in exactly the same manner, the system will perform a given task in half the time. [0007] Clock speeds are necessarily limited by various design parameters, and in particular are limited by signal propagation delays. In general, clock speeds can be increased if the length of signal paths is reduced, i.e., by shrinking the size of the logic elements. Early computer processors, which were constructed from many discrete components, were susceptible to significant speed improvements by shrinking component size, reducing discrete component numbers, and eventually, packaging the entire processor as an integrated circuit on a single chip. Modern processor chip designs often include one or more caches on the same integrated circuit chip as the processor, and in some cases include multiple processors on a single integrated circuit chip. [0008] Despite the enormous improvement in speed obtained from integrated circuitry, the demand for ever faster computer systems has continued. With this demand comes a need for even further size reduction in the logic circuitry within an integrated circuit chip. [0009] A typical integrated circuit chip is constructed in multiple layers. Many active and passive elements are formed on a substrate (usually silicon). A dielectric layer is placed over the elements, and multiple conductive layers, each separated by another dielectric layer, are formed over the elements. The conductive layers carry power and ground potentials, as well as numerous signal interconnects running among active elements. Each conductive layer comprises multiple discrete conductors, often running substantially in parallel. Conductive interconnects between conductive layers, or between a conductive layer and an active or passive element, are formed as holes in the dielectric layers, called vias, into which a conductive metal, such as aluminum or copper, is introduced. [0010] The number of active elements in a typical processor dictates a very large number of interconnections. A large number of relatively long, narrow conductors introduces some degree of parasitic capacitance in the integrated circuit, which varies with the individual conductors. As the number of such conductors increases and as processor clock speeds also increase, this parasitic capacitance becomes a significant problem for the designer. I.e., it becomes increasingly difficult to assure that all required signals will propagate the full length of their conductors and cause any required state change in an element at the opposite end within the available clock cycle time. [0011] The problem of parasitic capacitance has long been known by integrated circuit designers, and numerous design approaches have been used to counter its effects. For example, integrated circuits are laid out in such a manner as to reduce signal path lengths. Signal wires are laid out to avoid running wires for long distances next to each other in adjacent conductive layers. Intentional delays are sometimes introduced into certain paths to balance inherent delays of other paths. In some cases, long signal paths are split by clocking a signal into a latch, so that the signal requires multiple cycles to propagate. [0012] One of the fundamental physical parameters influencing the amount of capacitance in signal paths is the dielectric constant (k) of the dielectric material separating conductors. Ideally, the dielectric constant is as low as possible to reduce the amount of capacitance. However, it is not possible to simply select any arbitrary low-k material as a dielectric. Any material selected must provide suitable performance in numerous, demanding ways. For example, it must tolerate high temperatures of numerous processing steps, be extremely stable in operation, be compatible with other materials used as conductors and semiconductors, etc. [0013] Silica or silicon oxide or silicon dioxide (SiO.sub.2) has traditionally been the dielectric of choice, and modern semiconductor fabrication techniques have evolved as suitable for use with a silicon oxide dielectric. Silicon oxide has a dielectric constant in the high 3's to 4 range. Various alternative materials (having lower dielectric constants) have been proposed and/or have been the subject of investigation for use in integrated circuits. However, all such materials have their respective drawbacks, such as compatibility with existing processes or semiconductor materials. No single dielectric material has emerged as a clearly superior alternative to conventional silicon oxide. [0014] If a suitable dielectric could be found which both has substantially lower dielectric constant than conventional silicon oxide or similar materials, and is generally suitable as a substitute for silicon oxide, the parasitic capacitance of integrated circuits could be substantially reduced without any other design changes. Such a reduction would enable further clock speed enhancements and/or density of elements within an integrated circuit chip. A need therefore exists for an improved dielectric for use in integrated circuitry. SUMMARY OF THE INVENTION [0015] A dielectric structure (preferably as a layer of an integrated circuit chip) is formed by creating oriented cylindrical voids in a conventional dielectric material, such as silicon oxide. The voids reduce the dielectric constant of the composite structure below that of a conventional solid dielectric. [0016] In the preferred embodiment, voids are formed by first forming multiple relatively long, thin carbon nanotubes on a surface of an integrated circuit wafer, by depositing a conventional dielectric (such as silicon oxide) on the surface to fill the area between the carbon nanotubes, and by then removing the carbon nanotubes to produce voids in the locations formerly occupied by the carbon nanotubes. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes for dielectric material. [0017] In the preferred embodiment, a random pattern of nickel particles is formed as a catalyst on a surface of the wafer. Carbon nanotubes are grown from the nickel catalyst, oriented substantially perpendicular to the surface. A dielectric is then deposited on the surface, covering the carbon nanotubes and the area between the carbon nanotubes. The wafer is then polished to expose the tips of the carbon nanotubes and to establish a desired thickness of dielectric. The carbon nanotubes in the dielectric can then be removed by ashing with ozone or oxygen plasma to leave voids in the dielectric structure. Various additional process steps, some of which may be optional, are further described herein. [0018] A layer of dielectric structure having voids therein can be used either as an insulative layer between two conductive layers in an integrated circuit, or as the insulative material within a conductive layer which isolates multiple discrete conductors in the conductive layer. In any of the various preferred embodiments, the dielectric structure including voids is suitably patterned by any conventional process to form multiple conductive paths and/or vias. Patterning may be performed either before or after the carbon nanotubes are removed. [0019] The use of a conventional dielectric material having numerous air voids, as described herein, provides a relatively low-k dielectric. Furthermore, because the material is conventional (e.g., silicon oxide), any of various conventional processes can be used for depositing, polishing, patterning, etching, or otherwise manufacturing the integrated circuit wafer. Carbon nanotubes can be grown very thin and elongated, in a dense pattern. Unlike certain previous attempts to introduce air voids into a dielectric material, the use of carbon nanotubes produces oriented cylindrical voids of sufficient number to substantially reduce the dielectric constant of the resultant structure, leaving a dielectric layer which is both structurally strong and can be constructed compatibly with conventional processes and with other structures in the integrated circuit. [0020] The details of the present invention, both as to its structure and operation, can best be understood in reference to the accompanying drawings, in which like reference numerals refer to like parts, and in which: Continue reading about Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes... Full patent description for Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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