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  Integrated circuit capacitor structureUSPTO Application #: 20070072319Title: Integrated circuit capacitor structure Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode. (end of abstract) Agent: Marger Johnson & Mccollom, P.C. - Portland, OR, US Inventors: Jeong-Hoon AHN, Kyungtae LEE, Mu-Kyung JUNG, Yong-Jun LEE USPTO Applicaton #: 20070072319 - Class: 438018000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, With Measuring Or Testing, Electrical Characteristic Sensed, Utilizing Integral Test Element The Patent Description & Claims data below is from USPTO Patent Application 20070072319. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATION [0001] This application is a Divisional of U.S. patent application Ser. No. 10/678,531, filed on Oct. 3, 2003, now pending, which claims priority from Korean Patent Application No. 2002-63477, filed Oct. 17, 2002, the disclosures of which are incorporated herein in their entirety by reference. TECHNICAL FIELD [0002] The present invention relates to an integrated circuit capacitor and, more specifically, to a metal-insulator-metal (MIM) capacitor structure. Such a structure is particularly advantageous to use in logic, analog, or circuits that include both Dynamic Random Access Memory (DRAM) and Merged DRAM and Logic (MDL) devices. BACKGROUND [0003] Several types of integrated circuit capacitors exist, which are classified according to their junction structures, such as metal-oxide-silicon (MOS) capacitors, pn junction capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and metal-insulator-metal (MIM) capacitors. In all of the above-listed capacitors except for MIM capacitors, at least one electrode is formed of monocrystalline silicon or polycrystalline silicon. However, physical characteristics of monocrystalline and polycrystalline silicon limit minimizing the amount of resistance of a capacitor electrode. In addition, when a bias voltage is applied to a monocrystalline or polycrystalline silicon electrode, depletion may occur, which can cause the applied voltage to become unstable. When this occurs, the capacitance of the silicon electrode cannot be maintained at a certain level. [0004] Using MIM capacitors has been proposed to address the varying capacitance problem, since capacitance of MIM capacitors does not depend on a bias voltage or temperature. MIM capacitors have a lower voltage coefficient of capacitance (VCC) and a lower temperature coefficient of capacitance (TCC) than other capacitor types. The VCC indicates variation of capacitance according to the changes in voltage and the TCC indicates variation of capacitance according to the changes in temperature. Because of having a low VCC and TCC, MIM capacitors have been particularly useful for fabricating analog products. More recently, MIM capacitors have been used to make mixed mode signal products and system-on-a-chip (SOC) products. For example, MIM capacitors have been widely employed in analog capacitors and filters for analog or mixed mode signal applications in wired or wireless communications, as decoupling capacitors for main processing unit boards, as high frequency radio-frequency (RF) capacitors, and in embedded DRAMs. [0005] FIGS. 1 and 2 are cross-sectional diagrams of two conventional MIM capacitors as taught by R. Liu et al., Proc. IITC, 111 (2000) and M. Armacost et al., Proc. IEDM, 157 (2000), respectively. Reference numerals 10 and 12 indicate MIM capacitors, and reference numerals 20, 30, 40, and 50 indicate a lower electrode, a dielectric layer, an upper electrode, and a capping layer, respectively. In addition, reference numerals C/P_20, C/P_40, C/H, D/D_20, D/D_40, and D/R indicate a lower electrode contact plug, an upper electrode contact plug, contact holes, a dual damascene wiring layer contacting a lower electrode, a dual damascene wiring layer contacting an upper electrode, and damascene regions, respectively. Other parts of the MIM capacitors 10 and 12 correspond to interlayer or other dielectric layers. [0006] In the MIM capacitor 10 shown in FIG. 1, the lower electrode 20 is electrically connected to a wiring layer (not shown) by the lower electrode contact plug C/P_20 and the upper electrode 40 is electrically connected to another wiring layer (not shown) by the upper electrode contact plug C/P_40. The lower electrode contact plug C/P_20 and the upper electrode contact plug C/P_40 are formed in their respective contact holes C/H having a high aspect ratio but different depths. Specifically, the C/H for the C/P_20 runs deeper than the C/H for the C/P_40, because the C/P 20 contacts the lower electrode 20. When forming the contact hole C/H, it is difficult to precisely control an etching process so as to stop the etching of C/H at the top surface of the upper electrode 40 and at the top surface of the lower electrode 20 simultaneously. Therefore, the upper electrode 40 must be formed to have a predetermined thickness so that it can endure an excessive etching process. However, as the thickness of the upper electrode 40 increases, the dielectric layer 30 under the upper electrode 40 is more likely to be exposed to an excessive etching process for patterning the upper electrode 40, and thus the lower electrode 20 may be exposed due to the dielectric layer 30, which is etched away. Therefore, the dielectric layer 30 must also be formed to have a predetermined thickness so that it can endure an excessive etching process, and this results in a decrease in the capacitance of the entire capacitor 10. [0007] In the MIM capacitor 12 shown in FIG. 2, the dual damascene wiring layer D/D_20 and the dual damascene wiring layer D/D_40 are electrically connected to the lower electrode 20 and the upper electrode 40, respectively. They are formed in their respective damascene regions D/R having a high aspect ratio but different depths. In order to obtain a sufficient margin for an etching process for forming the dual damascene region D/R, in which the dual damascene wiring layer D/D_40 is supposed to be formed, the thickness of the upper electrode 40 and the thickness of the dielectric layer 30 must be increased, which accompanies the decrease in the capacitance of the entire capacitor 12. [0008] In addition, there is a high probability of having a bad electrical contact occur due to byproducts, like polymer, generated during the formation of the contact holes C/H and the damascene regions D/R because they have a high aspect ratio. In other words, the manufacturing process of conventional MIM capacitors results in many disadvantages including limiting the capacitance of a capacitor. [0009] Embodiments of the invention address this and other limitations in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS [0010] The invention will be understood more fully from the detailed description given below and from the accompanying drawings of particular embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are to facilitate explanation and understanding. [0011] FIGS. 1 and 2 are cross-sectional diagrams of conventional MIM capacitors. [0012] FIG. 3 is an equivalent schematic circuit diagram of an MIM capacitor according to an embodiment of the present invention. [0013] FIG. 4 is an example layout diagram for forming the MIM capacitor according to the schematic diagram of FIG. 3. [0014] FIGS. 5-7 are cross-sectional diagrams of MIM capacitors formed according to the layout illustrated in FIG. 4. [0015] FIG. 8 is an example layout diagram for forming the MIM capacitor according to the schematic diagram of FIG. 3. [0016] FIGS. 9-11 are cross-sectional diagrams of MIM capacitors formed according to the layout illustrated in FIG. 8. [0017] FIGS. 12-13 are additional example layout diagrams for forming the MIM capacitor according to the schematic diagram of FIG. 3. [0018] FIG. 14 is an equivalent schematic circuit diagram of an MIM capacitor according to another embodiment of the invention. [0019] FIG. 15 is an example layout diagram for forming the MIM capacitor according to the schematic diagram of FIG. 14. [0020] FIG. 16 is another example layout diagram for forming the MIM capacitor according to the schematic diagram of FIG. 14. Continue reading... Full patent description for Integrated circuit capacitor structure Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Integrated circuit capacitor structure patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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