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Integrated circuit (ic) having ic floorplan silhouette-like power supply net, and sea of supply (sos) electronic design automation (eda) tool for designing same

Integrated circuit (ic) having ic floorplan silhouette-like power supply net, and sea of supply (sos) electronic design automation (eda) tool for designing same description/claims

The invention is in the field of Integrated Circuit (IC) design in general, and IC power supply net design in particular.

ICs ranging from ASICs to full custom ICs include a transistor embedded silicon based structure, and an interconnect structure with metal layers for power routing purposes, namely, the provision of an IC power supply net, and transistor interconnection purposes. An IC power supply net includes a power net for connection to the power ports (hereinafter denoted “VDD ports”) of an IC's power consuming entities (hereinafter denoted “PCEs”), and a ground net for connection to their ground ports (hereinafter denoted “GND ports”). PCEs include full custom macrocells, and standard cell placement areas and, since an IC can have a hierarchically designed structure, a PCE in a non-leaf layer may include lower layer PCEs. IC power routing starts with the provision of an initial IC floorplan with PCEs, and involves determining an IC power supply net physical layout, calculating the widths of the wires making up its power and ground nets, determining slot spread in the wires to satisfy IC fabrication requirements, passing an IC power supply net verification procedure, and if necessary, modifying the IC floorplan and/or the IC power supply net.

Generally speaking, a computer executable Sea of Supply (SoS) Electronic Design Automation (EDA) tool in accordance with the present invention is programmed to implement a novel methodology for automating the hitherto manual IC power routing design process to yield a so-called IC floorplan silhouette-like power supply net based on the following two principles: First, each net of an IC floorplan silhouette-like power supply net exclusively occupies a single metal layer (hereinafter denoted “supply layer”). And second, any area of a supply layer unoccupied by PCEs, areas reserved for interconnection purposes, and the like, is assigned to be metal filled hence the term “IC floorplan silhouette-like”. By virtue of this logical complement approach, the supply layers assigned for use as an IC floorplan silhouette-like power supply net are entirely occupied by either exempt areas or metal filled areas whereby the former are conceptually islands floating within a so-called Sea-of-Supply power net (hereinafter denoted “SoS power net”) and a so-called Sea-of-Supply ground net (hereinafter denoted “SoS ground net”). Moreover, an IC floorplan silhouette-like power supply net has identical SoS power and ground nets except possibly for the locations of their slots because of IC fabrication reasons.

An IC floorplan silhouette-like power supply net preferably occupies the two lowermost metal layers of an interconnect structure immediately overlying its underlying silicon based structure to minimize the need for vias for connecting PCEs thereto, however, other metal layers which may not necessarily be neighboring may also be equally employed as supply layers. The appearance of a SoS net depends on the degree to which its originating IC floorplan can be compacted taking into account the dimensions of its typically rectangular PCEs and other exempt areas. Highly compact IC floorplans with, say, a 90% area utilization, defined as the combined area of an IC floorplan's exempt areas divided by its total area, lead to SoS nets similar in appearance to conventional manually designed nets. However, a SoS net of a less compact IC floorplan having, say, a 70% area utilization, in all likelihood includes one or more very wide metal wires or more aptly termed metal tracts to convey the fact that they have smaller aspect ratios than metal wires.

To summarize, the present invention facilitates an efficient IC power routing design process by negating the need to manually design a layout, determine slot spread, and the like. Moreover, since the present invention can be readily applied to different IC floorplans having the same exempt areas with minimal manual design effort, an IC layout designer is empowered to conveniently test different IC floorplans to determine the optimal IC floorplan and its inherently rendered IC floorplan silhouette-like power supply net. The present invention also benefits ICs having an IC floorplan silhouette-like power supply net in accordance with the present invention since PCEs can be readily provided with several VDD ports and GND ports along their horizontal and vertical edges for connection to a SoS power net and a SoS ground net, respectively, thereby rendering improved port accessibility. Furthermore, an IC having an IC floorplan silhouette-like power supply net enjoys lower noise levels. In this connection, it should be noted that an IC floorplan silhouette-like power supply net in accordance with the present invention may be designed using conventional EDA tools, for example, commercially available inter alia Synopsys, Inc., and Cadence, Inc.

In order to understand the invention and to see how it can be carried out in practice, a preferred embodiment will now be described, by way of a non-limiting example only, with reference to the accompanying drawings, in which similar parts are likewise numbered, and in which:

FIG. 1 is a block diagram of a computer executable Sea of Supply (SoS) Electronic Design Automation (EDA) tool for designing an IC floorplan silhouette-like power supply net;

FIG. 2A is a schematic representation of a save ring with non-slotted save ring vertices;

FIG. 2B is a schematic representation showing the non-slotted inner ring of a save ring surrounding a PCE with an internal power supply ring;

FIG. 2C is a schematic representation showing the non-slotted regions arising from the close proximity of a pair of PCEs;

FIG. 2D is a schematic representation showing the non-slotted regions arising from a pair of PCEs which are in even closer proximity than those of FIG. 2C;

FIG. 3A is a schematic representation showing a grid placed on an IC floorplan as employed by a minus union algorithm implemented by the SoS EDA tool of the present invention;

FIG. 3B is a schematic representation showing the merging of contiguous grid rectangles in the horizontal direction as effected by the minus union algorithm;

FIG. 3C is a schematic representation showing the merging of contiguous grid rectangles in the vertical direction as effected by the minus union algorithm;

FIG. 4 is a top level flow diagram showing the steps for designing an IC floorplan silhouette-like power supply net in accordance with the present invention;

FIG. 5 is a schematic representation of a highly simplified IC floorplan; and

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