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Information storage medium, information reproducing apparatus, and information reproducing methodRelated Patent Categories: Data Processing: Presentation Processing Of Document, Operator Interface Processing, And Screen Saver Display Processing, Presentation Processing Of Document, Synchronization Of Diverse MediaInformation storage medium, information reproducing apparatus, and information reproducing method description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070174759, Information storage medium, information reproducing apparatus, and information reproducing method. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATION [0001] This application is entitled to the benefit of U.S. Provisional Patent Application Ser. No. 60,757,847 filed on Jan. 11, 2006, which is incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] Orthogonal Frequency Division Multiple Access (OFDMA) technology is getting very popular in modern communication systems since the OFDMA technology can efficiently support multiple mobile stations with limited bandwidth and easily provide Quality of Service (QoS). The OFDMA technology is a multiple access version of orthogonal frequency-division multiplexing (OFDM). OFDM is a modulation technique for data transmission based on frequency-division multiplexing (FDM), which uses different frequency channels to transmit multiple streams of data. In OFDM systems, a wide channel is divided into multiple narrow-band subcarriers, which allow orthogonal modulated streams of data to be transmitted in parallel on the subcarriers. [0003] In OFDMA systems, multiple subscribers can simultaneously use different subcarriers for signal transmission. Thus, in an OFDMA system, multiple data bursts can be transmitted from a base station to multiple mobile stations in the same time frame but allocated in different frequency subcarriers. Consequently, an OFDMA system can support multiple mobile stations using different subcarriers. [0004] In a conventional OFDMA transmitter, outgoing data is processed for wireless transmission as OFDMA signals, including being forward error correction encoded. Under the mobile WiMAX standard, the outgoing data can be encoded using a tail-biting convolutional encoding scheme. Thus, in an OFDMA receiver, the incoming OFDMA signals must be decoded using an appropriate decoding technique to extract the original data in the signals. One of the techniques to decode the incoming convolutional-encoded OFDMA signals is Viterbi decoding. However, Viterbi decoding has been applied in the past to situations where the initial and final states of the encoded signals were known to the receiver. Under the mobile WiMAX standard, the initial and final states are unknown to the receiver. The only information known to the receiver is that the initial and final states of the encoded signals are the same. Thus, conventional Viterbi decoding techniques are not appropriate to decode tail-biting convolutional encoded signals under the mobile WiMAX standard. [0005] In view of this requirement, there is a need for a decoder and method for decoding a tail-biting convolutional encoded signal using Viterbi decoding scheme, where the initial and final states of the encoded signals are unknown. SUMMARY OF THE INVENTION [0006] A decoder and method for decoding a tail-biting convolutional encoded signal using Viterbi decoding scheme performs a traceback operation for a first portion of a total code block, which includes a code block of the tail-biting convolutional encoded signal and a padded block. During the traceback operation for the first portion, a particular state at a predefined position within the first portion is stored as a circular state. The circular state is used as a traceback starting state for at least one subsequent portion of the total code block to produce a decoded signal of the code block. The use of the circular state facilitates decoding of the code block even though the initial and final states of the code block are unknown. Since the traceback operation is performed on portions of the total code block rather than the entire total code block, the required memory for storing state metric information can be significantly reduced. [0007] A method for decoding a tail-biting convolutional encoded signal using Viterbi decoding scheme in accordance with an embodiment of the invention comprises receiving a code block of the tail-biting convolutional encoded signal and a padded block, the padded block being at least a portion of the code block, the code block and the padded block being parts of a total code block, performing an add-compare-select operation on the total code block to compute state metric information, performing a traceback operation for a first portion of the total code block using the state metric information, including storing a particular state at a predefined position within the first portion as a circular state, and performing the traceback operation for at least one subsequent portion of the total code block using the circular state as a traceback starting state, including selectively executing bit decisions for the at least one subsequent portion to produce a decoded signal of the code block. [0008] A decoder for decoding a tail-biting convolutional encoded signal using Viterbi decoding scheme in accordance with an embodiment of the invention comprises an add-compare-select unit, memory and a traceback unit. The add-compare-select unit is configured to perform an add-compare-select operation on a total code block to compute state metric information for the total code block. The total code block includes a code block of the tail-biting convolutional encoded signal and a padded block. The padded block includes at least a portion of the code block. The memory is operably connected to the add-compare-select unit to store the state metric information. The traceback unit is operably connected to the memory. The traceback unit is configured to perform a traceback operation on a first portion of the total code block using the state metric information. The traceback unit is further configured to store a particular state at a predefined position within the first portion during the traceback operation for the first portion as a circular state. The traceback unit is further configured to perform the traceback operation for at least one subsequent portion of the total code block using the circular state as a traceback starting state. The traceback unit is further configured to selectively execute bit decisions for the at least one subsequent portion to produce a decoded signal of the code block. [0009] Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrated by way of example of the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [0010] FIG. 1 is a block diagram of a decoder for decoding a tail-biting convolutional encoded signal in accordance with an embodiment of the invention. [0011] FIG. 2 is a block diagram of a tail-biting convolutional encoder. [0012] FIG. 3 illustrates a decoding operation of the decoder when the length of a code block being decoded is greater than the length of a padded block in accordance with an embodiment of the invention. [0013] FIG. 4 illustrates a decoding operation of the decoder when the length of a code block being decoded is less than the length of a padded block in accordance with an embodiment of the invention. [0014] FIG. 5 is a process flow diagram of a method for decoding a tail-biting convolutional encoded signal using Viterbi decoding scheme in accordance with an embodiment of the invention. DETAILED DESCRIPTION [0015] With reference to FIG. 1, a decoder 100 in accordance with an embodiment of the invention is shown. The decoder 100 operates to decode signals that have been encoded using a tail-biting convolutional encoding for forward error correction (FEC). The decoder 100 uses a Viterbi decoding scheme to decode a tail-biting convolutional encoded signal in which the initial and final states of the encoded signal are unknown. As described in more detail below, the decoder 100 is designed to perform a Viterbi-based decoding that quickly converges to the correct initial state, which reduces decoding delay. Furthermore, the decoder 100 is designed so that the required memory for decoding is reduced. The decoder 100 can be used in an Orthogonal Frequency Division Multiple (OFDM) based receiver, such as an Orthogonal Frequency Division Multiple Access (OFDMA) receiver. [0016] Tail-biting convolutional encoded signals are encoded using a convolutional encoder, such as an encoder 200 shown in FIG. 2. The encoder 200 includes a set of shift registers D.sub.1, D.sub.2 . . . D.sub.v-1 and adders. If a sequence of N information bits b.sub.0, b.sub.1 . . . b.sub.N-1 is to be encoded, where bo is encoded first and b.sub.N-1 is encoded last, the encoder 200 starts the encoding process by first filling up the delay elements, i.e., the shift registers D.sub.1, D.sub.2 . . . D.sub.v-1, from left to right with the final v-1 information bits b.sub.N-1, b.sub.N-2 . . . b.sub.N-(.sub.v-1) before encoding begins. Thus, the initial shift register contents, before encoding begins, are {D.sub.1, D.sub.2 . . . D.sub.v-1}={b.sub.N-1, b.sub.N-2 . . . b.sub.N-(.sub.v-1)}. The g.sub.x and g.sub.y sequence shown in FIG. 2 indicate the status of connections to each shift register (i.e, g=1 if there is a connection and g=0 otherwise) for outputs x and y, respectively. Since the final v-1 information bits b.sub.N-1, b.sub.N-2 . . . b.sub.N-(.sub.v-1) are again in the shift registers D.sub.1, D.sub.2 . . . D.sub.v-1 when the last information bit b.sub.N-1 is fed into the encoder 200, the final shift register contents equal the initial shift register contents. Therefore, the initial and final states of the encoded signal are forced to the same state. However, these initial and final states are known only at the transmitter. The only information known to the receiver is that the initial and final states of the encoded signal are the same, which presents a challenge when decoding the encoded signal. [0017] Turning back to FIG. 1, the decoder 100 includes a first memory 102, an add-compare-select (ACS) unit 104, a second memory 106, a traceback unit 108 and control logic 110. The first memory 102 is used to store at least one single code block 112 to be decoded. The length of the code block 112 equals the number of information bits in a single bit sequence before encoding. The ACS unit 104 is configured to perform an ACS operation on a total code block, which includes the code block 112 and a state converge block. The state converge block is a circularly padded block derived from the received code block 112. The length of the state converge block may vary. In some situations, the state converge block may be a small portion of the received code block 112. In other situations, the state converge block may be longer than the received code block 112. The ACS operation performed by the ACS unit 104 is a well-known process of Viterbi decoding, and thus, is not described herein in detail. The ACS operation involves computing state metric information 114 such as state metrics or surviving-branch decisions, which include probabilities of states with respect to reliability at each decision node. The state metric information produced by the ACS unit 104 is stored in the second memory 106 as the ACS operation on the total code block is performed. [0018] The traceback unit 108 of the decoder 100 is configured to perform traceback operations on predefined portions of the total code block using a sliding window, which may have a fixed or variable length, as the ACS operation is being performed on the total code block. As described in more detail below, the traceback unit 108 makes bit decisions during a traceback operation on a section of the total code block only if that section has been traced back during a previous traceback operation, which results in more accurate bit decisions. Furthermore, the traceback unit 108 uses a circular state as the traceback starting state for the last decoding portion of the total block state. That is, the circular state is forced as the traceback starting state for the last decoding portion of the total block state. A circular state is the best or optimal state (i.e., the state with the highest probability with respect to reliability) for a predefined position of the total code block, which corresponds to the beginning of the last decoding portion of the total code block. In an embodiment, the circular state is determined during the traceback operation for a first portion of the total code block. This circular state may be used as the traceback stating state for the last traceback portion of the total code block. Alternatively, the circular state may be updated during the traceback operation for one or more subsequent traceback portions of the total block. The latest up-to-date circular state can then be used as the traceback starting state for the last traceback portion of the total code block. [0019] The control logic 110 of the decoder 100 is configured to control the overall decoding process. In particular, the control logic 110 controls the data transmitted from the first memory 102 to the ACS unit 104. Thus, the control logic 110 determines the total code block, which includes a code block and a padded block, to be processed by the ACS unit 104. Consequently, the length of the total code block is determined by the control logic 110. The control logic 110 also controls when the traceback unit 108 performs a traceback operation so that predefined portions of the total code block are traced back. Continue reading about Information storage medium, information reproducing apparatus, and information reproducing method... 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