| High temperature operating package and circuit design -> Monitor Keywords |
|
|
  High temperature operating package and circuit designUSPTO Application #: 20080054496Title: High temperature operating package and circuit design Abstract: The invention provides a semiconductor device that is thermally isolated from the printed circuit board such that the device operates at a higher temperature and radiates heat away from the printed circuit board. In another embodiment, the semiconductor is stacked onto a second device and optionally thermally isolated from the second device. (end of abstract) Agent: Hiscock & Barclay, LLP - Rochester, NY, US Inventors: Neill Thornton, Dennis Lang USPTO Applicaton #: 20080054496 - Class: 257788 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080054496. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001]This invention relates to semiconductor devices and packages therefor designed to operate at high temperatures. The invention further relates to the stacking of power switching semiconductor devices. BACKGROUND OF THE INVENTION [0002]Conventionally, packages for semiconductor devices, such as power devices or integrated circuits, are designed to conduct the heat generated by the device to the printed circuit board (PCB). The heat is conducted through the die pad and the leads to the PCB, which dissipates the heat. High power devices, however, may operate at temperatures that may be out of the safe temperature range of the PCB. For example, silicon carbide (SiC) has desirable properties for high power devices, though SiC-based devices may operate at over 200.degree. C. Typically, a PCB is kept at temperatures below 100.degree. C. Therefore, a package that may operate at high temperatures without significantly affecting the PCB is desired. [0003]In certain cases, high power semiconductor devices provide good switching at high voltages, though they may be less effective at preventing leakage when the device is deactivated. For example, as described above, SiC is known to have desirable switching properties in high-voltage devices; however, SiC devices tend to leak current more readily than is desirable. Therefore, a circuit design that prevents leakage in high power devices and allows a high temperature device to be used without significantly affecting other devices is desired. SUMMARY OF THE INVENTION [0004]The invention comprises, in one form thereof, a circuit design and a package for semiconductor devices that reduces thermal conduction to the printed circuit board (PCB) in order to radiate the heat generated by the device away from the PCB. In one embodiment, the package is configured with the die pad at the top of the package, facing away from the PCB. The terminals of the die are electrically connected to the leads, which are located proximate to the PCB, via bond wires with low thermal conductivity. The die, the die pad, and the bond wires are encapsulated in a thermally resistant material that has a high thermal impedance as compared to certain metals, such as copper. Since the die is substantially thermally isolated from the PCB, the die operates at a high temperature and radiates heat away from the PCB. In a second embodiment, a high temperature power device is stacked on a second power device with a high thermal resistance layer therebetween. The circuit is configured such that the second power device is turned on before the high temperature device and turned off just after. This is accomplished by using a common gate drive and setting the threshold voltage of the second device to be lower than the threshold voltage of the high temperature device. Alternatively, a gate timing circuit is used to control the switches. [0005]More particularly, the invention includes a packaged semiconductor device, comprising an encapsulant having a top surface and a bottom surface, the encapsulant comprising a thermally resistant material; a die having a first surface and a second surface and being embedded in the encapsulant proximate to the top surface; a plurality of leads engaging the encapsulant proximate the bottom surface; and a die pad embedded in the top surface of the encapsulant. The die pad includes a die attach surface in engagement with the second surface of the die and at least one surface that is exposed by said encapsulant. The die attach surface of the die pad may be in electrical communication with the second surface of the die, which may be a field effect transistor with one or more drain terminals on the second surface. Alternatively, the die may be an integrated circuit. In a particular embodiment, the die is comprised of silicon carbide. The leads are connected to a printed circuit board such that the bottom surface of the encapsulant is proximate the printed circuit board. [0006]In another form, the invention includes a method for forming a package for a semiconductor device having a high temperature operation. The method comprises the steps of providing a semiconductor die attached to a die pad and vertically displaced from a plurality of leads; electrically connecting each of said leads to a terminal on said die via bond wires; encapsulating the die, the bond wires, at least a portion of the die pad, and at least a portion of the leads in a thermally resistant material; and attaching the leads to a circuit, which may comprise a printed circuit board, such that the die and the die pad are displaced from the circuit and substantially thermally isolated from the circuit. The die may be a field effect transistor having a drain terminal in electrical communication with the die pad, or, alternatively, the die is an integrated circuit. Further, the die may comprise silicon carbide. [0007]In another form, the invention includes a circuit having a thermally isolated semiconductor device. The circuit comprises a first semiconductor die having a first die top surface and a first die bottom surface; a second semiconductor die having a second die top surface and a second die bottom surface, the first die bottom surface being attached to the second die top surface; a thermal resistance layer which could be a die attachment material situated between the first die and the second die; and a die pad having a die attach surface engaging the second die bottom surface. In a particular embodiment, each of the first die and the second die are a field effect transistor wherein: the first die comprises a first die source terminal and a first die gate terminal on the first die top surface and a first die drain terminal on the first die bottom surface; and the second die comprises a second die source terminal and a second die gate terminal on the second die top surface and a second die drain terminal on the second die bottom surface. Further, the thermal resistance layer is electrically conductive such that the first die drain terminal is in electrical communication with the second die source terminal to connect the first die and the second die in series. Even further, the first die gate terminal and the second die gate terminal are in electrical communication with a common gate drive and the second die has a lower threshold voltage than the first die. Alternatively the first die gate terminal and the second die gate terminal are electrically connected to a gate timing circuit for controlling the activation and the deactivation of the first die and the second die. The thermal resistance layer may be an electrically conductive epoxy, a tungsten layer, or another suitable material that is thermally resistant and electrically conductive. The first die may comprise silicon carbide and the second die may comprise silicon. In an alternative embodiment, at least one of the first die and the second die may be an integrated circuit. [0008]In yet another form, the invention includes a method for providing a semiconductor power device with current leakage prevention. The method comprises the steps of providing a first field effect transistor (FET) die with a first FET gate terminal and a first FET source terminal on a first FET top surface and a first FET drain terminal on a first FET bottom surface; providing a second FET die with a second FET gate terminal and a second FET source terminal on a second FET top surface and a second FET drain terminal on a second FET bottom surface, wherein the second FET has a lower threshold voltage that the first FET; attaching the first FET die to the second FET die with an electrically conductive thermal resistance layer therebetween such that the first FET drain terminal is in electrical communication with the second FET source terminal; and affixing the second FET die to a die pad. The method may further comprise the step of connecting the first FET gate terminal and the second FET gate terminal to a common gate drive. [0009]In still another form, the invention includes a circuit comprising a plurality of semiconductor power devices configured in a stack and connected in series. The circuit may further comprise a thermal resistance layer between at least two of the plurality of semiconductor power devices. One or more of the semiconductor power devices may be field effect transistors and one or more of the semiconductor power devices may comprise silicon carbide. [0010]An advantage of the present invention is that the package provides a poor thermal path to the circuit board causing the device to operate at a higher temperature and to radiate heat away from the PCB. A further advantage of the invention is that it provides a high power switch stacked on top of and connected in series with another switch that control s the leakage current of the high power switch. Because the switches are separated by a thermal resistance layer, the high voltage device operates at a higher temperature without affecting the low temperature devices including the second switch and the PCB. BRIEF DESCRIPTION OF THE DRAWINGS [0011]The present invention is disclosed with reference to the accompanying drawings, wherein: [0012]FIG. 1 is a sectional view of the high temperature operating package of the first embodiment of the present invention; [0013]FIG. 2 is a sectional view of the high temperature operating package of the second embodiment; and [0014]FIG. 3 is an example circuit diagram of a circuit according to the package of FIG. 2. [0015]Corresponding reference characters indicate corresponding parts throughout the several views. The examples set out herein illustrate several embodiments of the invention but should not be construed as limiting the scope of the invention in any manner. DETAILED DESCRIPTION [0016]Referring to FIG. 1, there is shown the high temperature operating package of the present invention. The package 10 includes a semiconductor die 12, a die pad 14, a plurality of leads 16, and an encapsulant 18. [0017]As shown in FIG. 1, the die 12 is a semiconductor power device such as a field effect transistor. The invention, however, may be applied to any semiconductor device including an integrated circuit. The die 12 is made of any semiconductor material, however, silicon carbide (SiC) has been shown to have good performance characteristics at high temperatures. In the illustrated configuration, a first surface 20 of the die 12 includes terminals for the gate and the source and a second surface 22 includes one or more terminals for the drain. The second surface 22 is attached to a die attach surface 24 of the die pad 14 such as with an electrically conductive epoxy, solder, or another suitable method that provides electrical communication between the one or more drain terminals of the second surface 22 and the die attach surface 24. Several leads 16 are vertically spaced from the die 12 and the die pad 14, and wire bonds 28 electrically connect each of the leads 16 to one of the gate terminals, the source terminals, or the die pad 12, which is in communication with the drain terminal. [0018]The encapsulant 18 has a bottom surface 30 and a top surface 32 and is a material that has both a high electrical and thermal resistance in comparison to the metal components. A thermally resistant material, as used herein, is a material with a substantially higher thermal impedance than certain metals, such as copper. The leads 16 are proximate the bottom surface 30 such that the bottom surface 30 is proximate to the printed circuit board (PCB) when the leads 16 are connected to the PCB. The die pad 14 is situated at the top surface 32 with an exposed surface 26 uncovered by the encapsulant 18. The encapsulant material between the die 12 and the leads 16 and the PCB provides a poor thermal path from the die to the PCB. It should be noted that the bond wires 28 are thin and also provide a poor thermal path between the die 12 and the leads 16. [0019]In construction, the leads 16 and the die pad 14 may be provided in a lead frame that is separated after encapsulation. Also, the package 10 may be provided in a leadless configuration wherein the leads 16 are enclosed by the encapsulant 18 with one or more exposed surfaces. Continue reading... Full patent description for High temperature operating package and circuit design Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this High temperature operating package and circuit design patent application. Patent Applications in related categories: 20080197514 - Die coat perimeter to enhance semiconductor reliability - A semiconductor packaging stress relief technique with enhanced reliability. Reliability is enhanced over conventional post wirebond assembly die coating processes by forming a peripheral wall on the semiconductor die isolating the stress sensitive area from remaining area in the semiconductor die, and depositing die coat material constraining the flow of ... ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like High temperature operating package and circuit design or other areas of interest. ### Previous Patent Application: Ic package Next Patent Application: Vented cap humidification system Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the High temperature operating package and circuit design patent info. IP-related news and info Results in 0.34737 seconds Other interesting Feshpatents.com categories: Qualcomm , Schering-Plough , Schlumberger , Seagate , Siemens , Texas Instruments , |
||
