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High sensitivity and high dynamic-range cmos image sensor pixel structure with dynamic c-v characteristicsRelated Patent Categories: Radiant Energy, Photocells; Circuits And Apparatus, Photocell Controlled CircuitHigh sensitivity and high dynamic-range cmos image sensor pixel structure with dynamic c-v characteristics description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070252073, High sensitivity and high dynamic-range cmos image sensor pixel structure with dynamic c-v characteristics. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a pixel structure and novel operational characteristics for high performance CMOS Image Sensors. More specifically, the present invention relates to a novel electrical operation of the dynamic C-V characteristic with a transition voltage, which can be controlled by varying the photogate bias voltage, for high sensitivity and high dynamic-range performance using a new photogate pixel structure in high-end digital still cameras and high performance digital video cameras. [0003] 2. Description of the Related Art [0004] Today, advances and improvements continue to be made in the growing digital imaging world. Apart from the existing applications in fax machines, scanners, security cameras and camcorders, new markets are emerging in the consumer imaging industry such as digital still cameras, toys and PC cameras, cameras for cell phones and PDAs, biometrics, and automobiles. [0005] The two main silicon-based image sensor technologies are charge-coupled devices (CCDs) and CMOS image sensors (CISs). Up until the mid-1990s, CCDs have been the dominant technology in the imaging world, while traditional ICs are fabricated with the CMOS technology. Since then, however, there has been a growing interest in the development of CMOS image sensors in the [1]. ([1]: E. R. Fossum et al, "CMOS image sensors: Electronic camera-on-a-chip," IEEE Transactions on Electron Devices, vol. 44, No. 10, pp. 1689-1698, October 1997) The first CCD was reported by Bell Labs in 1970. [0006] It was adopted over other solid-state image sensors, including CIS, because of its reduced fixed pattern noise (FPN) and smaller pixel size. In the thirty years since its inception, CCD image sensors have attracted much of the research and development, thus achieving a very high level of performance with low readout noise, high dynamic range, and excellent responsivity. [0007] At the same time, however, the functional limitations of CCDs have also become apparent. CCD fabrication process does not allow cost-efficient integration of on-chip ancillary circuits such as signal processors, and analog-to-digital converters (ADCs). [0008] As a result, a CCD-based camera system requires not one image sensor chip, but a set of chips, which increases power consumption and hampers miniaturization of cameras. Consequently, the resurgence in CIS development is primarily motivated by the demand for an alternative imaging technology offering low cost, low power, high miniaturization, and increased functionality. [0009] The research and development activities in the past ten years have resulted in significant advances in CIS, offering performance as competitive as CCD, but with increased functionality and lower power consumption. Circuit techniques have been introduced on-chip to reduce FPN and enhance dynamic-range. [0010] In addition, the advancement and miniaturization of CMOS technology, driven by the tremendous growth in digital IC market, has outpaced similar improvements in CCD technology [2]. ([2]: E. R. Fossum et al, "Digital camera system on a chip," IEEE Micro, vol. 18(3), pp. 8-15, May-June 1998) [0011] On the other hand, technology and device scaling does not always lead to better image sensor performance [3]. ([3]: H. S. Wong et al, "Technology and device scaling considerations for CMOS imagers," IEEE Transactions on Electron Devices, vol. 43(12), pp. 2131-2142, December 1996) The PN junction photodiode, commonly used in CISs, is the simplest photodetecting device and is easily integrated in a standard digital CMOS process. [0012] Photodiode-based image sensors, however, suffer from low responsivity to input light. Thus, the main obstacle of CIS systems comes from the unscalability and low responsivity of the photosensor. The challenge then is to develop photodetectors and pixel architectures that potentially eliminate these device and process limitations. [0013] Recently, the CIS, which is the dominant image sensor, has been used in a wide variety of applications, including digital still camera, optical mouse, and mobile phones. The CAPS usually consists of a 3-transistor (3-T) pixel or a 4-transistor (4-T) pixel. The pinned photodiode (PPD) based 4-T pixel structure has been favorably used in the CAPS due to the performance advantages of low dark current and high sensitivity compared to the 3-T pixel structure [4]. ([4]: H. Abe et al, "Device technologies for high quality and smaller pixel in CCD and CMOS image sensors," in IEDM Dig. Tech. Papers, 2004, pp. 989-992) [0014] However, the PPD based 4-T pixel has some disadvantages, such as a small fill factor arising from the use of additional transistors, a low dynamic range associated with the small well capacity, and high cost due to the required modification in the typical logic process [5]. ([5]: H. Takahashi et al, "A 3.9-.mu.m pixel pitch VGA format 10-b digital output CMOS image sensor with 1.5 transistor/pixel," IEEE J. Solid-State Circuits, vol. 39, pp. 2417-2425, December 2004) SUMMARY OF THE INVENTION [0015] In this work, a new pixel structure is proposed and implemented based on a 3-T pixel structure using a standard 0.35-.mu.m CMOS logic process, which can improve not only the dynamic range but also the sensitivity at low illumination intensity. [0016] For the desired performance characteristics of the proposed pixel structure, a new photogate structure is incorporated into the photodiode active-pixel structure. The proposed pixel structure exhibits the dynamic integration capacitance (C.sub.int) characteristics, which can be controlled by varying the control-voltage at the photogate node (V.sub.PG). Since the sensitivity is inversely proportional to C.sub.int, the dynamic characteristics of C.sub.int can provide the new functionality and controllability for high sensitivity and high dynamic range. [0017] At a low voltage level of the photogate (V.sub.PG=0V), the pixel sensitivity of the new photogate pixel structure is maximized due to the minimum value of C.sub.int, leading to high sensitivity with more than two-times improvement compared to the conventional pixel. At a high voltage of V.sub.PG=3V, the dynamic range of the new structure can be maximized due to the increased well capacity with improvement more than 10 dB. Consequently, the new pixel structure allows performance tunability as well as optimization in both the dynamic range and the sensitivity of the image sensor cell. BRIEF DESCRIPTION OF THE DRAWINGS [0018] FIG. 1 is a drawing of the schematic circuit diagram of the 3-T pixel structure. [0019] FIG. 2(a) is a drawing of the conceptual circuit diagram of the proposed photogate pixel structure. [0020] FIG. 2(b) is a drawing of the schematic C-V characteristics at the integration node (V.sub.int) of the proposed photogate pixel structure, which can be controlled by varying the photogate bias voltage. [0021] FIG. 3 is a drawing of the layout diagram of the proposed pixel structure. Continue reading about High sensitivity and high dynamic-range cmos image sensor pixel structure with dynamic c-v characteristics... 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