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  High performance tapered varactorUSPTO Application #: 20070200161Title: High performance tapered varactor Abstract: Disclosed is a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. The fabrication of semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode. (end of abstract) Agent: Scully, Scott, Murphy & Presser, P.C. - Garden City, NY, US Inventor: Edward J. Nowak USPTO Applicaton #: 20070200161 - Class: 257312000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Insulated Gate Capacitor Or Insulated Gate Transistor Combined With Capacitor (e.g., Dynamic Memory Cell), Voltage Variable Capacitor (i. E., Capacitance Varies With Applied Voltage) The Patent Description & Claims data below is from USPTO Patent Application 20070200161. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention generally relates to semiconductor devices and to methods of fabricating semiconductor devices. More specifically, the invention relates to the formation of a high performance varactor on silicon in the manufacture of integrated circuit devices. [0003] 2. Background Art [0004] Varactors are voltage variable capacitors. These devices are essential for the design of key radio frequency (RF) CMOS and BiCMOS circuits, and are specifically used as tuning elements in voltage controlled oscillators (VCCs), phase shifters, phase-locked loop (PLL) circuits, and frequency multipliers. [0005] In general, varactor designs must maximize a number of properties. One is "tunability," which is the ratio between the highest and lowest capacitive values (Cmax/Cmin) over the range of applied voltages for the circuit. Another is "linearity." There are two definitions of `linearity`: 1/sqrt(C) and d(LnC)/dV, where C is the voltage-dependent varactor capacitance. In the first case it is desired that 1/sqrt(C) be a straight line, and in the second, that d(LnC)/dV be a constant, both as V varies. Yet another property is "Q," or quality factor, which a function of the series resistance of the diode and the capacitive value of the varactor at the higher frequency ranges of the circuit. [0006] In order to enhance the capacitive swing of a varactor, it also known to vary the dopant concentration of one or both of the diffused electrodes of the diode such that the diffusion has a retrograde dopant profile (that is, the dopant concentration is higher at the lower portion of the diffusion region than it is in the top). These so-called "hyperabrupt" junctions greatly increase the change in varactor capacitance for a given voltage swing. [0007] In practice, it has proven to be difficult to simultaneously enhance tunability, linearity, and Q of a varactor when integrated into a CMOS or BiCMOS process. For example, considering the PFET source/drain junction and well as a varactor device, additional n-well implants will decrease the well resistance and increase varactor Q, but will decrease varactor tuning range by making the source/drain p-n junction depletion regions smaller. [0008] Accordingly, a need has developed in the art for a varactor design that optimizes the tradeoffs between all of these properties, particularly when integrated into a process for forming other integrated circuit devices. SUMMARY OF THE INVENTION [0009] An object of this invention is to improve varactors in integrated circuit devices. [0010] Another object of the present invention is to provide a varactor having improved Cmax/Cmin with low series resistance. [0011] A further object of the invention is to use FinFET technology to provide a varactor having improved Cmax/Cmin and low series resistance. [0012] These and other objectives are attained with a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Preferably, this depletion zone includes a narrower portion and a wider portion. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. This results in low resistance to a contact at the end of the depletion zone. As the voltage of a gate of the varactor is moved further into depletion, the fully depleted portion of the depletion zone advances, decreasing the effective area of the capacitor. [0013] The fabrication of the semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode. [0014] Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [0015] FIG. 1 is a top view showing a varactor embodying the present invention. [0016] FIG. 2 is a side view taken along line A-A' of FIG. 1. [0017] FIG. 3 is a side view taken along line B-B' of FIG. 1. [0018] FIG. 4 shows a varactor embodying this invention and having a charge-neutral n-well of a given size. [0019] FIG. 5 shows the varactor of FIG. 4 with a smaller charge-neutral n-well. [0020] FIG. 5A shows a varactor embodying the present invention and with a curved surface. [0021] FIG. 6 illustrates a substrate structure that may be used in the fabrication of the varactor of FIGS. 1-5. Continue reading... Full patent description for High performance tapered varactor Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this High performance tapered varactor patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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