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  High-performance risc-dspUSPTO Application #: 20070239967Title: High-performance risc-dsp Abstract: A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seamless transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions of RISC instruction sets. The DSP superscalar architecture also provides memory pointers with hardware circular buffer support, an interruptible and nested zero-overhead loop counter, and prioritized low overhead interrupts. (end of abstract) Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c. - Washington, DC, US Inventors: William J. Dally, W. Patrick Hays, Robert Gelinas, Sol Katzman, Sam Rosen, Staffan Ericsson USPTO Applicaton #: 20070239967 - Class: 712035000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Processing Architecture, Microprocessor Or Multichip Or Multimodule Processor Having Sequential Program Control, Including Coprocessor, Digital Signal Processor The Patent Description & Claims data below is from USPTO Patent Application 20070239967. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. patent application Ser. No. 09/637,500, filed Aug. 11, 2000, which is incorporated herein by reference in its entirety, and which claims the benefit of U.S. Provisional Application No. 60/148,652, filed Aug. 13, 1999. FIELD OF THE INVENTION [0002] The present invention relates to digital signal processor (DSP) architectures. BACKGROUND OF THE INVENTION [0003] With the increasing commercial importance of DSP-intensive applications, such as wireless communication, modems, and computer telephony, has come an increasing recognition of the benefit of implementing DSP functions on a CPU. Not only are CPUs usually needed for memory management, user interface and Internet Protocol software, CPUs also have excellent third-party software tool support. [0004] Implementing certain DSP algorithms, such as the FIR Filter or Discrete Cosine Transform (DC7), in software, however, may degrade performance up to an order of magnitude as compared to specialized DSPs. Another difficulty is the problem of deterministic real-time allocation in sophisticated CPUs. [0005] Some vendors have tried to address these problems by offering auxiliary processing components. DSP coprocessors, for example, use separate instruction sets, instruction stores and execution units, and DSP accelerators share the same I-stream with the CPU but have separate execution units. These approaches, however, impose a substantial burden on the CPU in managing DSP functions. SUMMARY OF THE INVENTION [0006] Systems and methods consistent with the present invention provide for an alternate DSP architecture configuration that allows for more efficient implementation of DSP algorithms and use of CPU resources. [0007] A digital signal processor consistent with this invention comprises two execution pipelines capable of executing RISC instructions; instruction fetch logic that simultaneously fetches two instructions and routes them to respective pipelines; and control logic to allow the pipelines to operate independently. [0008] Another digital signal processor consistent with this invention and capable of integrating subopcodes into an established CPU instruction set comprises a memory that stores instructions having opcodes; an instruction decoder that identifies a relocatable opcode to designate subopcodes; and a subopcode detector that decodes subopcodes if the instruction decoder identifies the relocatable opcode. [0009] Still another digital signal processor consistent with this invention comprises a register pair; and means for executing a multiply instruction on a number stored in the register pair, including first means for performing multiply instructions on higher-order portions of each register in the register pair, second means for performing multiply instructions on the remaining portions of each register in the register pair, and third means for combining the results from the first and second means. [0010] A circular buffer control circuit consistent with this invention comprises a first number of circular buffer start registers; a first number of circular buffer end registers, each associated with a different one of the circular buffer start registers; and circular buffer control logic including means for comparing a pointer to an address in a selected one of the circular buffer end registers, and means for restoring the address in the one of the circular buffer start registers associated with the selected circular buffer end register if the pointer matches the address in the selected circular buffer end register. BRIEF DESCRIPTION OF THE DRAWINGS [0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one embodiment of the invention and, together with the description, serve to explain the objects, advantages, and principles of the invention. In the drawings: [0012] FIG. 1 is a block diagram of a DSP architecture consistent with this invention; [0013] FIG. 2 is a data flow diagram of the superscalar instruction issue consistent with this invention; [0014] FIG. 3 is a table indicating the instruction select logic consistent with this invention; [0015] FIG. 4 shows a superscalar RALU datapath consistent with this invention; [0016] FIG. 5 shows an example of a MMD register consistent with this invention; [0017] FIG. 6 is an illustration of a dual MAC datapath consistent with this invention; [0018] FIGS. 7A, 7B, and 7C show some of the data arithmetic modes; [0019] FIGS. 8A, 8B, 8C, and 8D contain a table of the instructions supported by an implementation consistent with this invention; Continue reading... Full patent description for High-performance risc-dsp Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this High-performance risc-dsp patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like High-performance risc-dsp or other areas of interest. ### Previous Patent Application: Self-contained processor subsystem as component for system-on-chip design Next Patent Application: Data processing system having bit exact instructions and methods therefor Industry Class: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) ### FreshPatents.com Support Thank you for viewing the High-performance risc-dsp patent info. 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