| High performance cmos circuits, and methods for fabricating the same -> Monitor Keywords |
|
|
  High performance cmos circuits, and methods for fabricating the sameRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Insulated Gate Field Effect Transistor In Integrated Circuit, Complementary Insulated Gate Field Effect TransistorsThe Patent Description & Claims data below is from USPTO Patent Application 20070152276. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention generally relates to semiconductor devices, such as high performance complementary metal-oxide-semiconductor (CMOS) circuits, that each contains at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). More specifically, the present invention relates to CMOS circuits that each contains at least one n-FET gate stack having a gate dielectric layer and a metallic gate conductor, and at least one p-FET gate stack having a gate dielectric layer and a silicon-containing gate conductor, as well as to methods for forming such CMOS circuits. BACKGROUND OF THE INVENTION [0002] In standard CMOS technology, an n-FET device uses an As (or other donor) doped n-type polysilicon layer as a gate electrode, which is deposited on top of a semiconductor oxide or semiconductor oxynitride gate dielectric layer. The gate voltage is applied through this n-doped polysilicon layer to create an inversion channel in the p-type silicon underneath the gate dielectric layer. Similarly, a p-FET device uses a boron (or other donor) doped p-type polysilicon layer as a gate electrode, which is also deposited on top of a semiconductor oxide or semiconductor oxynitride gate dielectric layer. The gate voltage is applied through the p-doped polysilicon layer to create an inversion channel in the n-type silicon underneath the gate dielectric layer. [0003] However, limitations of polysilicon gate electrodes are inhibiting further gains in the CMOS device performance. Future generations of device logic will be required to use replacement materials for the gate electrodes. [0004] Specifically, metallic materials have been shown as promising gate electrode materials for achieving further gains in device performance. [0005] However, integration of the metallic gate electrodes into the CMOS circuits has proven challenging. Specifically, for alternatives to the conventional gate structures (i.e., comprising p-doped and n-doped polysilicon gate electrodes) to be fully realized, the n-FET and p-FET devices of the CMOS circuits must comprise different metals, and complimentary metals with work functions that are equivalent to the p-doped and n-doped polysilicon gate electrodes must be integrated simultaneously to form the respective n-FET and p-FET gate structures in the CMOS circuits. Patterning, thermal budget restraints, and material interactions associated with front-end-of-line (FEOL) logic integration have been problematic for a number of candidate metal materials. [0006] As the industry struggles to find metal solutions for the p-FET and n-FET gate structures, there is a need for CMOS circuits that contain heterogeneous n-FET and p-FET gate structures for achieving continuous gains in the CMOS device performance. SUMMARY OF THE INVENTION [0007] The present invention, in one aspect, relates to a semiconductor device comprising: [0008] a semiconductor substrate containing at least first and second device regions adjacent to each other; [0009] a first gate stack located over the first device region, wherein the first gate stack comprises at least, from bottom to top, a gate dielectric layer comprising a dielectric material having a dielectric constant (k) equal to or greater than that of silicon dioxide, a metallic gate conductor, and a silicon-containing gate conductor; and [0010] a second gate stack located over the second device region, wherein the second gate stack comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. [0011] The term "metallic" as used herein refers to a structure or component that is formed essentially of a conductive material containing at least one metal in an elemental form, an alloy form, or a compound form. Examples of such conductive material include, but are not limited to: elemental metals, metal alloys, metal nitrides, metal silicides, etc. Preferably, the metallic gate conductor of the first gate stack comprises a metal nitride or a metal silicon nitride that contains a Group IVB or VB metal. More preferably, the metallic gate conductor comprises TiN, TaN, a ternary alloy of Ti--La--N, a ternary alloy of Ta--La--N, or a stack with a ternary alloy of Ti--La--N and Ta--La--N. [0012] Preferably, but not necessarily, the gate dielectric layer of the first gate stack comprises a hafnium-based dielectric material selected from the group consisting of hafnium oxide, hafnium silicate, hafnium silicon oxynitride, a mixture of hafnium oxide and zirconium oxide, and multilayers thereof. [0013] The metallic gate conductor of the first gate stack preferably comprises a metal nitride or a metal silicon nitride that contains a Group IVB or VB metal. More preferably, the metallic gate conductor comprises TiN, TaN, a ternary alloy of Ti-RE-N (RE stands for rare earth metal), a ternary alloy of Ta-RE-N, a ternary alloy of Ti-AE-N (AE stands for alkaline earth metal), a ternary alloy of Ta-AE-N, or a stack containing mixtures thereof. [0014] The silicon-containing gate conductors of the first and second gate stacks preferably comprise polycrystalline silicon. [0015] The first and second gate stacks as described hereinabove constitute a basic heterogeneous gate configuration for the semiconductor device of the present invention. Such first and second gate stacks may comprise one or more additional layers for further improvements of the device performance or manufacturability in the present invention. [0016] For example, the first gate stack may further comprise an interfacial layer located beneath the gate dielectric layer and an additional silicon-containing gate conductor located above the silicon-containing gate conductor, and the second gate stack may further comprise an additional silicon-containing gate conductor located above the silicon-containing gate conductor. [0017] For another example, the first gate dielectric stack may further comprise a conductive oxygen barrier layer located above the metallic gate conductor and beneath the silicon-containing gate conductor. [0018] For yet another example, the first gate dielectric stack may further comprise an interfacial layer located beneath the gate dielectric layer, and a rare earth metal-containing or an alkaline earth metal-containing layer located above, or within, the gate dielectric layer and underneath the metallic gate conductor. If the first gate dielectric stack comprises a rare earth metal-containing layer, the rare earth metal-containing layer preferably comprises an oxide or nitride of at least one rare earth metal. Alternatively, if the first gate dielectric stack comprises a alkaline earth metal-containing layer, the alkaline earth metal-containing layer preferably comprises a compound having the formula M.sub.xA.sub.y, wherein M is at least one alkaline earth metal, and wherein A is one of O, S, orahalide, x is 1 or 2, and y is 1, 2 or 3. [0019] In another aspect, the present invention relates to a method for forming the semiconductor device with the basic heterogeneous gate configuration (i.e., without any additional layer), comprising: [0020] forming a first gate dielectric layer and a silicon-containing gate conductor selectively over the second device region of the semiconductor substrate; [0021] forming a protective capping layer selectively over the second device region; Continue reading... Full patent description for High performance cmos circuits, and methods for fabricating the same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this High performance cmos circuits, and methods for fabricating the same patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like High performance cmos circuits, and methods for fabricating the same or other areas of interest. ### Previous Patent Application: Devices without current crowding effect at the finger's ends Next Patent Application: Mos field-effect transistor and manufacturing method thereof Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the High performance cmos circuits, and methods for fabricating the same patent info. IP-related news and info Results in 0.27462 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , |
||
