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High dynamic range analog to digital converter architectureHigh dynamic range analog to digital converter architecture description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070188364, High dynamic range analog to digital converter architecture. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] The present invention relates generally to data communication systems. More particularly, the present invention relates to an analog-to-digital converter architecture. BACKGROUND [0002] The prior art includes many analog-to-digital converter ("ADC") designs. An ADC receives an analog input signal and generates a digital representation of the magnitude of the analog input signal. Any practical ADC exhibits limited dynamic range and spur-free dynamic range. This limit is imposed by the dynamic range of the analog circuitry utilized by the ADC, basic quantum physics related to the quantum noise of the electronic circuits, and the quantization noise associated with the finite number of bits produced by the ADC. Some conventional ADC devices employ a sigma delta technique to extend their dynamic range. Sigma delta techniques predict a sample as being nearly equivalent to the previous sample, and digitally shape the quantization noise to avoid interfering with the desired signal. Sigma delta techniques utilize digital filtering to suppress quantization noise in the region of the signal of interest by constructing a digital feedback path at the frequency of interest. Although sigma delta techniques can improve the dynamic range of a basic ADC design, some applications may have ADC dynamic range requirements that exceed conventional ADC devices that incorporate sigma delta noise feedback. [0003] Accordingly, it is desirable to have an ADC architecture that extends the dynamic range and bandwidth of conventional ADCs. In addition, it is desirable to have an ADC technology that is capable of detecting low power waveforms, and secondary waveforms that may otherwise be "hidden" in a primary or strong waveform. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background. BRIEF SUMMARY [0004] An ADC configured in accordance with an example embodiment of the invention has a high dynamic range relative to conventional ADCs. The ADC described herein extends its dynamic range by measuring, predicting, and subtracting predicable high power waveform components from the signal to be digitized. As a result, the available dynamic range of a finite bit ADC can be applied to the remaining less predicable or lower power signal components. The predicted waveform can be added to the measured waveform, resulting in a representation of the entire composite signal. [0005] The above and other aspects of the invention may be carried out in one form by an ADC architecture comprising an ADC having a positive input for a first analog signal, a negative input for a second analog signal, and an ADC output, where the ADC is configured to generate a first digital output at the ADC output, and the first digital output is generated in response to the first analog signal and the second analog signal; a processor having an input coupled to the ADC output, and having a first output for a digital adjustment signal, where the processor includes a waveform prediction module configured to determine predictable signal characteristics of the first analog signal, and to generate the digital adjustment signal in response to the predictable signal characteristics; and a digital-to-analog converter ("DAC") coupled between the first output of the processor and the negative input of the ADC. The DAC is configured to generate the second analog signal in response to the digital adjustment signal. BRIEF DESCRIPTION OF THE DRAWINGS [0006] A more complete understanding of the present invention may be derived by referring to the detailed description and claims when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures. [0007] FIG. 1 is a graph of magnitude versus frequency for signal content that may be received by an ADC; [0008] FIG. 2 is a schematic representation of an ADC architecture configured in accordance with an example embodiment of the invention; [0009] FIG. 3 is a schematic representation of a communication system configured in accordance with an example embodiment of the invention; and [0010] FIG. 4 is a flow chart of an analog-to-digital conversion process according to an example embodiment of the invention. DETAILED DESCRIPTION [0011] The following detailed description is merely illustrative in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description. [0012] The invention may be described herein in terms of functional and/or logical block components and various processing steps. It should be appreciated that such block components may be realized by any number of hardware, software, and/or firmware components configured to perform the specified functions. For example, an embodiment of the invention may employ various integrated circuit components, e.g., memory elements, digital signal processing elements, logic elements, look-up tables, or the like, which may carry out a variety of functions under the control of one or more microprocessors or other control devices. In addition, those skilled in the art will appreciate that the present invention may be practiced in conjunction with any number of data transmission protocols and that the system described herein is merely one exemplary application for the invention. [0013] For the sake of brevity, conventional techniques related to signal processing, data transmission, analog-to-digital conversion, digital-to-analog conversion, waveform prediction, sigma delta noise feedback, and other functional aspects of the systems (and the individual operating components of the systems) may not be described in detail herein. Furthermore, the connecting lines shown in the various figures contained herein are intended to represent example functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in a practical embodiment. [0014] The following description refers to elements or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/feature is directly joined to (or directly communicates with) another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, "coupled" means that one element/feature is directly or indirectly joined to (or directly or indirectly communicates with) another element/feature, and not necessarily mechanically. Thus, although the schematics shown in FIG. 2 and FIG. 3 depict example arrangements of elements, additional intervening elements, devices, features, or components may be present in actual embodiments (assuming that the functionality of the circuits is not adversely affected). [0015] Those of skill in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the following description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. [0016] An ADC architecture as described herein is particularly suited for use with analog signals that may be a composite of more than one signal, e.g., signals originating from different sources, signals having different characteristics, a desired signal mixed with noise, or the like. For example, FIG. 1 is a graph of magnitude versus frequency for signal content 100 that may be received by an ADC architecture. Signal content 100 is generally characterized by a carrier frequency of about 1880 MHz and a noise floor that hovers at approximately -90 dBc. Although not a requirement or limitation of the invention, signal content 100 has the characteristics of a typical OFDM waveform, namely, signal content 100 includes a noticeable pedestal of energy (identified by reference number 102) that is a few dBc above the noise floor on either side of the primary energy peak. In practice, however, this pedestal of energy may be caused by a relatively weak received signal component that is in the presence of a relatively strong received signal component. In some practical applications, such as a cellular telephone system where a strong signal may be interfering with a weak signal, it may be desirable to actually receive the weak signal component. An ADC architecture utilized by the cell phone receiver may have difficulty with the weak signal component due to the practical dynamic range limitations of the ADC device. [0017] A standard ADC device has a usable dynamic range of about 60 dB. Thus, it can be difficult to accurately process a weak signal component that is more than 60 dB lower than a strong signal component. An enhanced ADC device that utilizes sigma delta noise feedback techniques may have an extended dynamic range of almost 80 dB. Although this is a measurable improvement over standard ADC devices, some practical applications may require more than 80 dB of dynamic range. [0018] An ADC architecture configured in accordance with an example embodiment of the invention utilizes a traditional ADC device, a gain control device, processing logic that predicts the strong signal components of an input waveform, and a DAC device. The ADC architecture synthesizes the strong waveform components in an appropriate manner such that the strong predictable components can be subtracted from the input signal prior to digitization. The prediction procedure may employ estimation or prediction software that is specifically configured according to certain known types of strong signal interference. For example, in radar applications, the prediction algorithm may be suitably configured with the ability to predict a pulse at a given power level and repetition rate. In radio communication applications, the prediction algorithm may be suitably configured with the ability to subtract a strong narrowband continuous wave interference signal (essentially, a sine wave of relatively constant amplitude, frequency, and phase). In speech communication applications, the prediction algorithm may be suitably configured with the ability to determine and subtract the predicable parts of a speech waveform from a nearby speaker, such that the speech waveform from a distant speaker can also be accurately captured. [0019] In practical embodiments, the first samples of the strong signal component cannot be accurately predicted because the ADC architecture has little or no a priori knowledge of the input signal characteristics. Accordingly, an ADC architecture configured in accordance with a practical implementation of the invention may perform a very brief training or initialization procedure to ensure that the strong signal component is accurately predicted. In addition, the input gain of the ADC architecture may be adjusted to prevent overflow. The ADC architecture may utilize a standard 14-bit ADC device, and the output of the ADC device may be registered into an overall output word having a larger number of bits (for example, 20 bits). In operation, as the digital circuitry becomes aware of what types of strong waveforms might be present (and, therefore, might be predictable), the circuitry begins to update magnitude, frequency, phase, pulse repetition frequency ("PRF") rate, or other signal properties on locally strong signals, and begins to predict those waveform components. As it predicts them, the ADC architecture synthesizes those waveform components in magnitude and phase so as to be able to subtract those components from the incoming signal, allowing the remaining unpredicted components to be converted into the digital domain with higher gain and, consequently, better resolution. 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