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High-density inter-die interconnect structureRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Device Or Circuit Responsive To Nonelectrical Signal, Responsive To Electromagnetic Radiation, Having Diverse Electrical Device, Charge Transfer Device (e.g., Ccd, Etc.)High-density inter-die interconnect structure description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060166395, High-density inter-die interconnect structure. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This patent application is a divisional application of and claims the benefit of the U.S. patent application assigned Ser. No. 10/638,248 and filed on Aug. 8, 2003, which is a continuation application of and claims the benefit of the U.S. patent application assigned Ser. No. 09/950,387 and filed on Sep. 10, 2001. FIELD OF THE INVENTION [0002] The present invention is directed to an interconnect structure for semiconductor die and, more specifically, the invention relates to an interconnect structure for die where the circuits on at least one die are separately and independently operable and closely spaced. BACKGROUND OF THE INVENTION [0003] Various types of imagers or image sensors are in use today, including charge-coupled device (CCD) image sensors and complementary metal-oxide semiconductor (CMOS) image sensors. These semiconductor-based image sensors are widely used in many image input devices because they can be mass produced using advanced fine-patterning lithographic techniques. Applications include digital cameras, computer peripherals for document capture, visual communications, and facsimile machines. [0004] A CCD image sensor utilizes an array of photo sensors to form charge packets proportional to the received light intensity. These photo sensors are typically photo transistors or photo diodes located on the image sensor surface. Each charge packet constitutes a pixel of the composite image. The image data is read out from the CCD array by shifting these analog charge packets from the CCD array interior to the periphery in a pixel-by-pixel manner. To begin the readout process, the charges on the first row are transferred to a readout register and from there the signals are input to an amplifier and in most applications to an analog-to-digital converter. Once a row has been read, its charges on the readout register row are deleted. The next row then enters the readout register and all the rows above move down one row. In this way, each row is read, one row at a time. Because all the pixels in a row of pixels are read simultaneously, the pixels of the CCD array are not individually addressable. [0005] Due to voltage, capacitance and process constraints, CCD arrays are not well suited to integration at the high levels of integration possible in CMOS integrated circuits. Hence, any supplemental signal processing circuitry required for the CCD image sensors (e.g., memory for storing information related to the sensor) is generally provided on one or more separate chips. As a result, the system cost and size are increased. It is also known that CCD image sensors require a large power consumption and higher operating voltages, as compared with conventional CMOS signal processing circuitry. [0006] CMOS image sensors typically utilize an array of active pixel image sensors and a row or register of amplifiers to sample and hold the output of a given row of pixel image sensors. The principle of a CMOS pixel's operation is based on the modulation of a reverse biased pn junction capacitance (of a diode, for example) due to impinging light. Photons absorbed in the depletion region of the reverse biased junction generate electron-hole pairs that discharge the reverse biased capacitance. Larger junctions collect more photons and are more sensitive to light, but larger junctions also reduce the resolution of a sensor because fewer pixels can be placed on the available surface area. [0007] CMOS image sensors have several advantages over CCD image sensors. CMOS image sensors are formed with the same CMOS process technology used for the associated circuitry required to operate the CMOS image sensor and therefore the sensors and support circuitry are easily integratible into a single chip. Single chip integration eases miniaturization, lowers manufacturing costs, and boosts reliability. Using CMOS image sensors, it is possible to create a monolithic integrated circuit providing not only the sensor but also control logic and timing, image processing, and signal-processing circuitry. Thus the CMOS image sensors can be manufactured at lower cost, relative to CCD image sensors, using conventional CMOS integrated circuit fabrication processes. Also, the CMOS image sensors operate at a lower operating voltage and consume less power, allowing the system into which the sensors are incorporated to operate longer on batteries, which is a major advantage for hand-held imaging products. Finally, each CMOS image sensor is accessible over a grid of x-y lines, instead of using the shift register process of charged coupled devices. The column and row addressability of the CMOS image sensor, which is similar to the conventional RAM readout process, allows windowing of the image. CMOS image sensors require only a single power supply to drive both the image sensor and the associated circuitry. By contrast, CCD image sensors typically require three different input voltages. Also, CCD image sensors lack a consistent dark level voltage due to fabrication processing imperfections. CMOS image sensors are also known to exhibit inconsistent dark levels, but the associated CMOS signal processing circuitry can track the dark level for each CMOS image sensor and provide a compensation factor during the signal processing function so that a uniform dark level is achievable across the CMOS image sensor array. [0008] However, CMOS image sensors are not without disadvantages. The use of state-of-the-art CMOS integrated circuit fabrication techniques for the associated signal processing circuitry, and the CMOS image sensor would compromise the construction of the CMOS photo sensors, thereby reducing the image signal quality. For example, typical substrate and source/drain doping levels (or retrograde doped tubs where the doping level at the surface is lower than the doping level below the surface) conventionally used in CMOS processes are higher than the doping levels that provide optimal image sensor quality. Reducing the doping levels to achieve better sensor sensitivity, dynamic range, or color balance, would significantly degrade the performance of the CMOS processing circuitry. Therefore, higher levels of component integration (i.e., image sensors and operative signal processing circuitry on the same chip) are therefore not practical. [0009] Further, in those situations where the CMOS image sensor and its signal processing circuitry are co-located on the same integrated circuit, the associated circuits consume a portion of the available pixel area, resulting in a larger overall chip area and reducing the image fill factor (the ratio of the active pixel area to the total pixel area). The efficiency, resolution and sensitivity of the CMOS image sensor array is in turn disadvantageously reduced. Also, certain CMOS material layers (e.g., salicide layers) may be partially or completely opaque, reducing the image sensor sensitivity. In an effort to overcome the disadvantages created when using state-of-the-art CMOS process technology in conjunction with CMOS image sensors, certain modified CMOS processes have been created that remove processing steps or alter device physical characteristics to improve the image sensor signal quality. Although removal of these process steps improves image sensor signal quality, the CMOS technology is generally compromised. In summary, it can be said that state-of-the-art CMOS image sensor processing technology lags by several generations the current state of the CMOS processing art. SUMMARY OF THE INVENTION [0010] To overcome the disadvantages discussed above relative to the use of CMOS image sensors and associated CMOS operative circuitry, the present invention provides an interconnect system between a first integrated circuit structure having a plurality of image sensors fabricated therein and a second CMOS (or other integrated circuit type, for example, BiCMOS) integrated circuit structure having signal processing circuitry operative in conjunction with the image sensors. With the separation of the image sensor structure and the operative signal processing circuitry, the image sensor structure can be fabricated with processing techniques that are specifically optimized for the image sensors, and the signal processing circuitry can also be fabricated with uniquely optimal fabrication techniques and device characteristics. The interconnect system comprises electroless nickel plated bumps, solder bumps or other well-known die interconnect structures, especially fine pitch interconnect structures. The bumps are provided on the image sensor structure for interconnecting each image sensor or pixel element with its associated signal processing circuitry located on a separate structure. Mating die interconnect structures are also included on the signal processing circuitry for connection to each of the pixel elements of the image sensor structure. After fabrication of the two individual structures, the image sensor structure is bonded to the signal processing structure by way of the mating die interconnect structures. According to the teachings of the present invention, the use of separate image sensor and signal processing structures allows the functional characteristics and processing methodology of each structure to be optimized by use of the most favorable fabrication processing steps and device characteristics. BRIEF DESCRIPTION OF THE DRAWINGS [0011] The present invention can be more easily understood and the further advantageous and uses thereof more readily apparent, when considered in view of the description of the preferred embodiments and the following figures in which: [0012] FIG. 1 illustrates a typical CMOS image sensor array; [0013] FIG. 2 illustrates a prior art CMOS image sensor circuit; [0014] FIG. 3 is a time line showing the operational phases of the CMOS image sensor circuit of FIG. 2; [0015] FIG. 4 is a cross-sectional view of first and second integrated circuit structures interconnected according to the teachings of the present invention; and [0016] FIG. 5 illustrates doping regions for the CMOS image sensor circuit. DESCRIPTION OF THE PREFERRED EMBODIMENTS [0017] The processing steps and hardware components of the present invention have been represented by conventional processes and elements in the drawings, showing only those specific details that are pertinent to the present invention so as not to obscure the disclosure with details that will be readily apparent to those skilled in the art having the benefit of the description herein. Exemplary device layers are not shown to scale. Like reference characters represent like structures elements throughout. [0018] Bulk semiconductor materials can be used as photo conductors (also referred to as photo sensors or image sensors) based on the change in the semiconductor resistance as a function of the wavelength and intensity of the impinging light waves. Electrons in bound states in the valence band (for intrinsic semiconductor material) or in doping-determined energy levels within the forbidden band gap (for extrinsic semiconductor materials) absorb energy from the incident light photons and are excited into free states in the conduction band. The electrons remain in the excited state for a characteristic lifetime. The conduction of electrical current takes place as a result of movement of the electrons in the conduction band or movement of the positive holes formed in the valence band. The resistance of the semiconductor material is thus inversely proportional to the illumination and this resistance change is translated into a change in the current that flows through the device output circuit. [0019] In lieu of simple semiconductor bulk photo sensors, photo sensor junction devices can be used to improve the speed of response and the sensitivity of the detector to optical radiation. Such two-terminal devices designed to respond to photon absorption are referred to as photodiodes. In a conventional reverse-biased diode, carriers generated within the depletion region drift away from the depletion region due to the electric field; electrons are therefore collected in the n region and holes in the p region. These carriers form the reverse current. Also, minority carriers generated thermally within a diffusion length of the edge of the transition region diffuse to the depletion region and are swept to the other side by the electric field. If the junction is also uniformly illuminated by photons having an energy greater than the semiconductor material band gap, then these electron-hole pairs also participate in the reverse current. This is the basic principle by which a reverse-biased diode detects light. Although electron-hole pairs are also generated outside the depletion region, they do not result in current flow. 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