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High bandwidth datapath load and test of multi-level memory cellsHigh bandwidth datapath load and test of multi-level memory cells description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060193172, High bandwidth datapath load and test of multi-level memory cells. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of U.S. patent application Ser. No. 10/335,961, filed on Dec. 31, 2002. BACKGROUND [0002] This invention relates generally to an apparatus and technique for testing of multi-level cells (MLC) in a memory storage device, and more particularly to a system that tests multi-level memory cells using a high bandwidth data path architecture. [0003] A typical memory storage device may include a number of memory cells, each capable of storing a zero or one bit. Memory cells may be grouped together in a memory cell array containing a pattern of zeros and ones. Data bits can be loaded into memory cell arrays by identifying a word made up of memory cells in the array and storing the expected data bits into the memory cells of the word. [0004] A memory cell may be tested by using an iterative test technique in which the memory cell is loaded with a reference zero or one bit pattern, the pattern read from the memory cell and compared against the reference value. Memory cell arrays similarly may be tested by loading reference sequences of ones and zeros into the array, reading the values stored in the memory cell array, and comparing them against the reference sequence. Exhaustive testing of a memory cell array including n memory cells requires testing all combinations of ones and zeros that may be stored in the memory cell array. Thus, up to 2.sup.n load/store tests described above may have to be performed to adequately test the memory cell array. Such exhaustive testing may be time consuming and costly, adding significantly to the final cost of the memory storage device. [0005] Another type of memory storage device may include multilevel cells (MLCs). Each MLC may have more than two logic levels. Due to its ability to indicate more than two logical states, multiple bits may be stored in each MLC. These multiple bits per cell create additional challenges for testing a memory storage device having MLCs. [0006] Thus, there is a continuing need for better ways to test an MLC memory that reduces test time and does not require increased hardware and die area. BRIEF DESCRIPTION OF THE DRAWINGS [0007] FIG. 1 is a block diagram of a portable computing or communication device including the MLC flash memory according to an embodiment of the invention. [0008] FIG. 2 is a schematic depiction of a MLC flash memory device showing hardware to program memory cells and perform test according to an embodiment of the invention; [0009] FIG. 3 is a schematic depiction of a program selection logic in the write interface logic according to an embodiment of the invention; [0010] FIGS. 4a and 4b are flow charts showing the MLC program technique that may be adapted to test the MLC flash memory device in accordance with an embodiment of the invention; [0011] FIG. 5 is a schematic depiction of a MLC flash memory device showing the command controller and test hardware according to an embodiment of the invention; and [0012] FIG. 6 is a flow chart showing a technique for testing of MLC flash memory cells in accordance with an embodiment of the invention. DETAILED DESCRIPTION [0013] Referring to FIG. 1, some embodiments 10 of a portable computing or communication device (called a "portable device 10" herein) includes an application subsystem 20 and a communication subsystem 40 that communicate via a communication link 50 of the device 10. As a more specific example, the portable device 10 may be a one-way pager, a two-way pager, a personal communication system (PCS), a personal digital assistant (PDA), a cellular telephone, a portable computer, etc. The application subsystem 20 provides features and capabilities that are visible and/or used by a user of the portable device 10. For example, the application subsystem 20 may be used for purposes of email, calendaring, audio, video, gaming, etc. The communication subsystem 40 may be used for purposes of providing wireless and/or wired communication with other networks, such as cellular networks, wireless local area networks, etc. [0014] For the case in which the portable device 10 is a cellular telephone, the application subsystem 20 may provide an interface to the user of the cellular telephone and thus, provide a keypad 22 which the user may use to enter instructions and telephone numbers into the cellular telephone; a display 24 for displaying command options, caller information, telephone numbers, etc.; and a microphone 26 for sensing commands and/or voice data from the user. The microphone 26 thus, may provide an analog signal indicative of a voice signal, and this analog signal may be converted into a digital format by an analog-to-digital converter (ADC) 32. The digital data from the ADC 32, in turn, is provided to an application processor 34 of the application subsystem 20. Likewise, data from the keypad 22 may also be provided to the application processor 34. Graphical data may be provided by the application processor 34 to the display 24 for viewing by the user of the cellular telephone. [0015] Among the other features of the application subsystem 20, the subsystem 20 may include a speaker 28 that receives an analog signal from a digital-to-analog converter (DAC) 30 that, in turn, receives digital data from the application processor 34. For example, the speaker 28 may be used to provide an audible ringing signal to the user, for the case in which the device 10 is a cellular telephone, as well as provide an audio stream for audio data that is provided by a cellular network, for example. [0016] The application subsystem 20 may also include a memory 141. As an example, this memory 141 may be a dynamic random access memory (DRAM) or, as shown in FIG. 1, a MLC flash memory, as just a few examples. The memory 141 is coupled to the application processor 34 for purposes of storing data, operating system code, application code, etc. that is executed by the application processor 34. As a more specific example, in some embodiments of the invention, the memory 141 may store boot instruction code that is executed by the application processor 34 for power-on-self-test purposes. The application subsystem 20 may also include an interface 33 for purposes of establishing a communication bridge between the communication link 50 and circuitry of the application subsystem 20. [0017] In some embodiments of the invention, the portable device 10 may include multiple communication subsystems, and in some embodiments of the invention, the portable device 10 may include multiple nodes that are coupled to the communication link 50. [0018] In some embodiments of the invention, the communication subsystem 40 includes a baseband processor 42 that establishes the particular communication standard for the device 10. For example, if the device 10 is a cellular telephone, the baseband processor 42 may establish a code division multiple access (CDMA) cellular radiotelephone communication system, or a wide-band CDMA (W-CDMA) radiotelephone communication system, as just a few examples. The W-CDMA specifically has been proposed as a solution to third generation ("3G") by the European Telecommunications Standards Institute (ETSI) as their proposal to the International Telecommunication Union (ITU) for International Mobile Telecommunications (IMT)-2000 for Future Public Land Mobile Telecommunications Systems (FPLMTS). [0019] The baseband processor 42 is coupled to a radio frequency/intermediate frequency (RF/IF) interface 48 that forms an analog interface for communicating with an antenna 49 of the device 10. A voltage controlled oscillator (VCO) 46 is coupled to the RF/IF interface 48 to provide signals having the appropriate frequencies for modulation and demodulation, and the baseband processor 42 controls the VCO 46 to regulate these frequencies, in some embodiments of the invention. [0020] Among the other features of the communication subsystem 40, in some embodiments of the invention, the subsystem 40 may include a memory 141 (a DRAM memory or, as shown in FIG. 1, a MLC flash memory, as a few examples) that is coupled to the baseband processor 42. The memory 141 may store program instructions and/or data. For example, in some embodiments of the invention, the memory 141 stores Basic-Input-Output-System (BIOS) code routines that are the low-level software interface with the hardware. Continue reading about High bandwidth datapath load and test of multi-level memory cells... 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