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  Hardware-generated and historically-based execution optimizationUSPTO Application #: 20070050608Title: Hardware-generated and historically-based execution optimization Abstract: Embodiments include a device, and a method. In an embodiment, a device includes a processor operable to execute an instruction set, a communications link exposed to an execution-optimization synthesizer and to the processor, and the execution-optimization synthesizer. The execution-optimization optimization synthesizer includes an execution-optimization synthesizer operable to collect data from the communications link that corresponds to an execution of at least one instruction of the instruction set, and generate an execution-optimization information utilizing the collected data from the communications link and corresponding to the execution of at least one instruction of the instruction set. (end of abstract) Agent: Searete LLC Clarence T. Tegreene - Bellevue, WA, US Inventors: Bran Ferren, W. Daniel Hillis, William Henry Mangione-Smith, Nathan P. Myhrvold, Clarence T. Tegreene, Lowell L. Wood USPTO Applicaton #: 20070050608 - Class: 712227000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Processing Control, Specialized Instruction Processing In Support Of Testing, Debugging, Emulation The Patent Description & Claims data below is from USPTO Patent Application 20070050608. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] The present application is related to, claims the earliest available effective filing date(s) from (e.g., claims earliest available priority dates for other than provisional patent applications; claims benefits under 35 USC .sctn.119(e) for provisional patent applications), and incorporates by reference in its entirety all subject matter of the following listed application(s) (the "Related Applications") to the extent such subject matter is not inconsistent herewith; the present application also claims the earliest available effective filing date(s) from, and also incorporates by reference in its entirety all subject matter of any and all parent, grandparent, great-grandparent, etc. applications of the Related Application(s) to the extent such subject matter is not inconsistent herewith. Related Applications [0002] 1. For purposes of the USPTO extra-statutory requirements, the present application constitutes a continuation-in-part of U.S. patent application entitled PROCESSOR RESOURCE MANAGEMENT, naming Bran Ferren; W. Daniel Hillis; Nathan P. Myhrvold; Clarence T. Tegreene; and Lowell L. Wood, Jr. as inventors, U.S. Ser. No. 11/214,449, filed Aug. 29, 2005. [0003] 2. For purposes of the USPTO extra-statutory requirements, the present application constitutes a continuation-in-part of U.S. patent application entitled MULTIPROCESSOR RESOURCE OPTIMIZATION, naming Bran Ferren; W. Daniel Hillis; Nathan P. Myhrvold; Clarence T. Tegreene; and Lowell L. Wood, Jr. as inventors, U.S. Ser. No. 11/214,458, filed Aug. 29, 2005. [0004] 3. For purposes of the USPTO extra-statutory requirements, the present application constitutes a continuation-in-part of U.S. patent application entitled PREDICTIVE PROCESSOR RESOURCE MANAGEMENT, naming Bran Ferren; W. Daniel Hillis; William Henry Mangione-Smith; Nathan P. Myhrvold; Clarence T. Tegreene; and Lowell L. Wood, Jr. as inventors, U.S. Ser. No. 11/214,459, filed Aug. 29, 2005. [0005] 4. For purposes of the USPTO extra-statutory requirements, the present application constitutes a continuation-in-part of U.S. patent application entitled RUNTIME-BASED OPTIMIZATION PROFILE, naming Bran Ferren; W. Daniel Hillis; William Henry Mangione-Smith; Nathan P. Myhrvold; Clarence T. Tegreene; and Lowell L. Wood, Jr. as inventors, U.S. Ser. No. ______, [Attorney Docket No. 0805-027-003B] filed Nov. 30, 2005. [0006] 5. For purposes of the USPTO extra-statutory requirements, the present application constitutes a continuation-in-part of U.S. patent application entitled ALTERATION OF EXECUTION OF A PROGRAM IN RESPONSE TO AN EXECUTION-OPTIMIZATION INFORMATION, naming Bran Ferren; W. Daniel Hillis; William Henry Mangione-Smith; Nathan P. Myhrvold; Clarence T. Tegreene; and Lowell L. Wood, Jr. as inventors, U.S. Ser. No. ______, [Attorney Docket No. 0805-027-003C] filed Nov. 30, 2005. [0007] 6. For purposes of the USPTO extra-statutory requirements, the present application constitutes a continuation-in-part of U.S. patent application entitled FETCH REROUTING IN RESPONSE TO AN EXECUTION-BASED OPTIMIZATION PROFILE, naming Bran Ferren; W. Daniel Hillis; William Henry Mangione-Smith; Nathan P. Myhrvold; Clarence T. Tegreene; and Lowell L. Wood, Jr. as inventors, U.S. Ser. No. ______, [Attorney Docket No. 0805-027-003D] filed Nov. 30, 2005. [0008] The United States Patent Office (USPTO) has published a notice to the effect that the USPTO's computer programs require that patent applicants reference both a serial number and indicate whether an application is a continuation or continuation in part. Stephen G. Kunin, Benefit of Prior-Filed Application, USPTO Electronic Official Gazette, Mar. 18, 2003 at http://www.uspto.gov/web/offices/com/sol/og/2003/week11/patbene.htm. The present applicant entity has provided a specific reference to the application(s)from which priority is being claimed as recited by statute. Applicant entity understands that the statute is unambiguous in its specific reference language and does not require either a serial number or any characterization such as "continuation" or "continuation-in-part." Notwithstanding the foregoing, applicant entity understands that the USPTO's computer programs have certain data entry requirements, and hence applicant entity is designating the present application as a continuation in part of its parent applications, but expressly points out that such designations are not to be construed in any way as any type of commentary and/or admission as to whether or not the present application contains any new matter in addition to the matter of its parent application(s). SUMMARY [0009] An embodiment provides a device. The device includes a processor operable to execute an instruction set, a communications link exposed to an execution-optimization synthesizer and to the processor, and the execution-optimization synthesizer. The execution-optimization synthesizer includes an execution-optimization synthesizer operable to collect data from the communications link that corresponds to an execution of at least one instruction of the instruction set, and generate an execution-optimization information utilizing the collected data from the communications link and corresponding to the execution of at least one instruction of the instruction set. In addition to the foregoing, other device embodiments are described in the claims, drawings, and text form a part of the present application. [0010] Another embodiment provides a method. The method includes collecting data corresponding to an execution of at least one instruction of an instruction set from a processor executing the at least one instruction of an instruction set. The method also includes creating an execution-optimization information utilizing the collected data corresponding to the execution of at least one instruction of the instruction set and which is usable in another execution of the at least one instruction of an instruction set. In addition to the foregoing, other method embodiments are described in the claims, drawings, and text form a part of the present application. [0011] A further embodiment provides a device. The device includes a first circuit for collecting data corresponding to a runtime execution of at least one instruction of an instruction set from a communications link that is transparent to software and exposed to a processor having a processor instruction set that includes the instruction set. The device also includes a second circuit for creating an execution-optimization information utilizing the collected data corresponding to the execution of at least one instruction of the instruction set and which is usable in another execution of the at least one instruction of an instruction set. The circuit for creating the execution-optimization information may include the circuit for collecting data corresponding to an execution. In addition to the foregoing, other device embodiments are described in the claims, drawings, and text form a part of the present application. [0012] An embodiment provides a device. The device includes a microengine operatively coupled with a processor having an instruction set. The microengine includes a microengine operable gather data in a manner transparent to software executing on the processor and corresponding to a runtime execution of at least a portion of the instruction set by the processor. The microengine is also operable to create a runtime-based optimization profile utilizing the gathered dynamic data and which is useable in a subsequent execution of the at least a portion of the instruction set by the processor. The device may include the processor having an instruction set. The device may include a communications link exposed to the microengine. The device may include a communications link exposed to the microengine and transparent to software executing on the processor. The device may include a communications link operably coupled to the microengine and to the processor. In addition to the foregoing, other device embodiments are described in the claims, drawings, and text form a part of the present application. [0013] Another embodiment provides a method implemented in a hardware device. The method includes gathering data corresponding to an execution of at least one instruction of an instruction set by a processor and in a manner transparent to software executing on the processor. The method also includes creating an execution-based optimization profile utilizing the gathered data and which is useable in a subsequent execution of the at least one instruction of the instruction set by the processor. The method may include saving the execution-based optimization profile. The method may include saving the execution-based optimization profile in an association with the at least one instruction of the instruction set. In addition to the foregoing, other method embodiments are described in the claims, drawings, and text form a part of the present application. [0014] A further embodiment provides a device. The device includes means for gathering data in a manner transparent to software executing on a processor and corresponding to an execution of at least one machine instruction of an instruction set by the processor. The device also includes means for creating an execution-based optimization profile utilizing the gathered data and which is useable in a subsequent execution of the at least one machine instruction of the instruction set by the processor. In addition to the foregoing, other device embodiments are described in the claims, drawings, and text form a part of the present application. [0015] An embodiment provides a device. The device includes an information store operable to save an execution-optimization information, a first processor, and a hardware circuit. The hardware circuit includes a hardware circuit for altering an execution of a program by the first processor in response to the execution-optimization information. The execution-optimization information being created by a hardware device utilizing data collected from a second processor and corresponding to a previous runtime execution by the second processor of at least a portion of the program that was transparent to any software executing on the second processor. The first processor and the hardware circuit may be formed on a single chip. In addition to the foregoing, other device embodiments are described in the claims, drawings, and text form a part of the present application. [0016] Another embodiment provides a method. The method includes identifying an instruction to be fetched for execution by a first processor, and altering an execution of the instruction to be fetched for execution in response to an execution-optimization information. The execution-optimization information previously generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor. In addition to the foregoing, other method embodiments are described in the claims, drawings, and text form a part of the present application. [0017] A further embodiment provides a device. The device includes means for identifying an instruction to be fetched from an instruction set of a program for execution by a first processor. The device also includes means for altering an execution of the instruction from the instruction set of a program in response to an execution-optimization information. The execution-optimization information having been generated by a hardware device utilizing data generated by a second processor, and which data corresponds to a previous real execution the instruction to be fetched from the instruction set of a program that was transparent to software executing on the second processor. In addition to the foregoing, other device embodiments are described in the claims, drawings, and text form a part of the present application. [0018] An embodiment provides a device. The device includes a processor operable to execute an instruction set, and an execution-optimization circuit. The execution circuit includes an execution circuit for receiving an identification of a first instruction to be fetched from the instruction set for execution by the processor, and for pointing to a second instruction of the instruction set of the processor to be fetched for execution by the processor if indicated by an execution-based optimization profile. The execution-based optimization profile being previously derived by a hardware device utilizing data invisible to software and generated during a runtime execution of at least a portion of the instruction set. The execution-optimization circuit may include at least one of a microengine, a micro-programmed circuit, and/or a hardwired circuit. In addition to the foregoing, other method embodiments are described in the claims, drawings, and text form a part of the present application. [0019] Another embodiment provides a method transparent to software executing on a processor. The method including fetching a second instruction for execution by the processor if indicated by an execution-based optimization profile in response to an identification of a first instruction to be fetched for execution by a processor. The execution-based optimization profile previously derived by a hardware device utilizing data invisible to software and generated during a runtime execution of at least a portion of the instruction set. The method may include identifying the first instruction to be fetched for execution by the processor. [0020] A further embodiment provides a device. The device includes means for selecting a first instruction to be fetched from an instruction set of a static program for execution by a processor. The device also includes means for routing the fetch of the first instruction to a second instruction of the instruction set of a static program if indicated by an execution-based optimization profile. The execution-based optimization profile having been derived from data invisible to software and generated during a historical execution of the static program. [0021] The foregoing is a summary and thus by necessity contains simplifications, generalizations and omissions of detail. Consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the devices and/or processes described herein, as defined by the claims, will become apparent by reference to the drawings and the following detailed description. Continue reading... Full patent description for Hardware-generated and historically-based execution optimization Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Hardware-generated and historically-based execution optimization patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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