| Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit -> Monitor Keywords |
|
|
 
Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuitRelated Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Testing Or EvaluatingGuided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20050273738, Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This application for an invention relates to U.S. Provisional Application Ser. No. 60/579,922 entitled RULES AND DIRECTIVES FOR VALIDATING CORRECT DATA USED IN THE DESIGN OF SEMICONDUCTOR PRODUCTS filed 15 Jun. 2004, and U.S. patent application Ser. No. ______ entitled RULES AND DIRECTIVES FOR VALIDATING CORRECT DA TA USED IN THE DESIGN OF SEMICONDUCTOR PRODUCTS, LSIL Docket 04-0977 filed 20 Dec. 2004 (referred to herein as a component of the TOOLS); it also relates to U.S. patent application filed on 6 May 2004 Ser. No. 10/840,534 entitled ASSURING CORRECT DA TA ENTRY TO GENERATE VIEWS FOR A SEMICONDUCTOR PLATFORM (referred to herein as a component of the TOOLS); and to U.S. Provisional Application Ser. No. 60/577,356 filed 3 Jun. 2004 and U.S. patent application Ser. No. ______, LSIL Docket No. 04-0824 entitled LANGUAGE AND TEMPLATE FOR USE IN THE DESIGN OF SEMICONDUCTOR PRODUCTS (referred to herein as a component of the TOOLS) filed 20 Dec. 2004, all applications owned by the same assignee as this application and all applications being incorporated by reference in their entireties. FIELD OF THE INVENTION [0002] This invention relates generally to the field of electronic circuit design and more particularly relates to a method, apparatus, and a computer program product by which clocks can be easily specified, generated, integrated and verified for a design flow of a semiconductor product. BACKGROUND [0003] An integrated circuit comprises layers of a semiconductor, usually silicon, with specific areas and specific layers having different concentrations of electron and hole carriers and/or insulators. The electrical conductivity of the layers and of the distinct areas within the layers are determined by the concentration of dopants within the area. In turn, these distinct areas interact with one another to form transistors, diodes, and other electronic devices. These specific transistors and other devices may interact with each other by field interactions or by direct electrical interconnections. Openings or windows are created for these electrical interconnections between the layers by a combination of masking, layering, and etching additional materials on top of the wafers. These electrical interconnections may be within the semiconductor or may lie above the semiconductor areas and layers using a complex mesh of conductive layers, usually metal such as platinum, gold, aluminum, tungsten, or copper, fabricated by deposition on the surface and selective removal, leaving the electrical interconnections. Insulative layers, e.g., silicon dioxide, may separate any of these semiconductor or connectivity layers. Depending upon the interconnection topology, transistors perform Boolean logic functions like AND, OR, NOT, NOR and are referred to as gates. [0004] Several types of integrated circuits have been developed that take advantage of a modular approach having areas in which the transistors and their respective functions are fixed and other areas in which the transistors and their functions are totally or partially programmable/customizable. The different proportion of fixed to programmable modules in an integrated circuit is limited by factors such as complexity, cost, time, and design constraints. The field programmable gate array (FPGA) refers to a type of logic chip that can be reprogrammed. Because of the programmable features, FPGAs are flexible and modification is almost trivial but, on the other hand, FPGAs are very expensive and have the largest die size. The relative disadvantage of FPGAs, however, is its high cost per function, low speed, and high power consumption. FPGAs are used primarily for prototyping integrated circuit designs but once the design is set, faster hard-wired chips are produced. Programmable gate arrays (PGAs) are also flexible in the number of possible applications that can be achieved but are not quite as flexible as the FPGAs and are more time-consuming to modify and test. An application specific integrated circuit (ASIC) is another type of chip designed for a particular application. ASICs are efficient in use of power compared to FPGAs and are quite inexpensive to manufacture at high volumes. ASICs, however, are very complex to design and prototype because of their speed and quality. Application Specific Standard Products (ASSPs) are hard-wired chips that meet a specific need but this customization is both time-consuming and costly. An example of an ASSP might be a microprocessor in a heart pacemaker. [0005] A digital system can be represented at different levels of abstraction to manage the description and design of complex systems with millions of logic gates, etc. For instance, a circuit diagram or a schematic of interconnected logic gates is a structural representation; a picture of a chip with pins extending from the black box/rectangle is a physical representation; and the architectural representation, considered the highest level of abstraction, describes a system in terms of what it does, how it behaves, and specifies the relationship between the input and output signals. An architectural description could be a list of functional units or operations and the nature of their interactions. Typical architectural representations may include such things as: (1) the performance characteristics of an interface, latency of access, or throughput; (2) protocols that form the mechanisms to facilitate the interactions, e.g., PCI bus to connect to external components or an AHB bus for interconnections on the chip, or custom interfaces, as required; (3) a listing of functions and possible mechanisms for implementation, such as a microprocessor block or memory controller, etc. Other abstract descriptions could be a Boolean expression or the data register transfer level logic (RTL). RTL descriptions are specified by the following three components: (1) the set of registers in the system or subsystem, such as a digital module; (2) the operations that are performed on the data stored in the registers; and (3) the control that supervises the sequence of the operations in the system. [0006] Specialized electronic design automation (EDA) software, referred to as tools, intended to implement a more efficient process to design chips has been introduced. Integrated circuits are now designed with the EDA tools using hardware description languages, typically Verilog or VHDL. VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language, the development of which was sponsored by the U.S. Department of Defense and the IEEE in the mid 1980s. VHDL and Verilog are only two hardware description languages but seem to have become the industry's standard languages to describe and simulate complex digital systems and incorporate timing specifications and gate delays, as well as describe the integrated circuit as a system of interconnected components. Execution of programs in hardware description languages are inherently parallel meaning that as soon as a new input arrives the commands corresponding to logic gates are executed in parallel. In this fashion, a VHDL or Verilog program mimics the behavior of a physical, usually digital, system. [0007] In spite of the implementation of EDA tools, chip designers and testers still manually define the specification for clocks and the specification and address mapping for individual registers and internal memory, as well as separately and manually specify the implementation at the RTL, the verification testcases, and the firmware header file. Maintaining consistency and manually editing the multitude of minute modifications often required by this out-dated and tedious approach is very difficult and conducive to many mistakes. Inserting clocks during the design of semiconductor chips is still approached in an ad hoc fashion with little regard to other key aspects of the design system. Clock specifications that embody the capabilities of a design system are more complex than the component and chip architect and RTL logic designer are aware; thus creating a clocking "specification" via RTL gates and timing constraints is a poor means of specification that does not account for the bounds of physical realization given a particular design flow. A logical design specification does not encompass all the physical design specifications, and the indirect specification process often used requires reverse engineering to gauge and check the original design intent often too late in the design process. Often neglected in the design of clocking systems are the actual design tools and processes that realize the specification. These neglected but key aspects result in an incomplete specification for the entire integrated circuit and significant redesign is often required to create logic that can be clocked within the bounds of the design flow. Sometimes, the actual clocking circuits must be significantly altered to allow effective physical realization; the original intent may not be able to be correctly reversed-engineered and, therefore, may actually be implemented incorrectly. Clock specifications for an entire semiconductor product or integrated circuit may be displayed in tabular form such as shown in FIG. 1 wherein parameters of the clock might be headings of columns and instances of a clock signal might be the rows. Typically there may be tens or hundreds of clocks per integrated circuit so a tabular view may have hundreds of rows with numerous columns. Changing a value of a clock parameter in one column might affect the value of a parameter in another column or may even be disallowed, let alone critically impact other components or functions not included in the clocking specification. In addition, different perspectives or views with which a user might be concerned, so the tabular format of clock specifications used today typically contains superfluous and irrelevant information when addressing a particular aspect or problem of integrating clocks in a semiconductor product. For example, when correcting for phase, timing, and relationships among two clock signals, it is distracting to have to weed through the myriad of other clocks, and other clocking parameters not affecting the phase, timing, and relationships of two particular clock signals. In any case, a chip designer or clock integrator is typically unaware of the change or the factors influencing or influenced by a modification she/me makes until much further along in the design process, such as simulation and/or testing, or maybe not detected even until manufacture of the chip at the waste of hundreds of thousands of dollars if a critical clock does not work as expected. [0008] There is thus a need in the industry to provide a user with tools and interfaces that intelligently guide a user in the specification, creation, and integration of clocks into a semiconductor platform or a semiconductor ASIC in the context of the entire or limited views of the design flow. SUMMARY OF THE INVENTION [0009] To satisfy this needs presented above, the inventors offer a method, a tool, and a program product to integrate clocks during the design of semiconductor products. The method comprises the steps of: reading an application set comprising a platform and a description of the platform; reading a customer's specification for an intended semiconductor product; visually displaying a plurality of views/perspectives of a clocking structure of the application set; for each of the views/perspectives, visually displaying and offering user interfaces to guide a user in the selection of parameters of the clock within the context of the view/perspective; and integrating the selected parameters, the customer's specification, and the application set into a design flow. In offering a designer only a contextual view/perspective and validating parameters entered by the designer, the method and the tool and program product create a design flow for the semiconductor product whose clocking and timing is correct-by-construction. The method, tool, and program displays and offers a designer only those parameters can be correctly realized by the specific design flow or a subset of that design flow. [0010] The contextual views/perspectives may be selected from the group comprising: a hierarchical view; an architectural view; a circuit diagram view; a timing view; a mode view; a cost view; a printing view; a power consumption view; a documentation view; and/or a tabular view wherein features of the above views may be combined and are displayed in each of the plurality of views/perspectives as it pertains to a context in a module and/or component. For example, one of the plurality of views/perspectives may comprise a hierarchical view illustrating an origination of a plurality of clocks and a throughput of each of the plurality of clocks through each of a plurality of logical modules in a semiconductor platform to be designed into a semiconductor product. Using the method and the tool and/or the program/product, a user is able to acquire scalable detail acquired pertaining to one or more of the following parameters: number of clocks, a path of the clocks, related clocks, the source of clocks from one or more oscillators, reset clocks, timing, phase. [0011] Another of the views/perspectives may comprise a display and offer the user a sequence of a plurality of elements comprising a clock factory, or a phase locked loop; one or more of the plurality of elements selected from the group comprising: a source multiplexer, a signal conditioner, a math function, an edge controller, a glitchless multiplexer, a root gate, a branch gate, timing, a reset, a test multiplexer, an inverter, a signal source input. [0012] The tool, method, and program product may further restrict or hide clocking parameters not affecting nor affected by the user choices. [0013] The invention may further be considered a tool for the design of semiconductor products, comprising: a reader to acquire a clocking specification of an application set to be developed into a semiconductor product; a customer's specification for the semiconductor product; a configurer to render the clocking specification into a plurality of scalable contextual perspectives, each of the scalable contextual perspective displaying portions of the clocking specification and the customer's specification relevant to its perspective; and a user interface within at least one scalable contextual perspective to guide a user to select at least one correct clocking parameter to integrate the customer's specification with the clocking specification of the application set. [0014] Other aspects and features of the present invention, as defined solely by the claims, will become apparent to those ordinarily skilled in the art upon review of the following non-limited detailed description of the invention in conjunction with the accompanying figures. BRIEF DESCRIPTION OF THE DRAWINGS [0015] FIG. 1 is a simplified table specifying a clock. [0016] FIG. 2 is block diagram of a networked computer system in which the clock specification, creation, and integration tool of the invention can be implemented. [0017] FIG. 3 is a simplified block diagram of the functional components within a computer workstation to which an integrated circuit developer may access and use the clock specification, creation, and integration tool in accordance with an embodiment of the invention. [0018] FIG. 4 is a simplified block diagram of a semiconductor platform having a number of components, each of which will probably have to be considered in terms of clocking, the clocks created and integrated according to an embodiment of the invention. [0019] FIG. 5 is a simplified diagram illustrating the hierarchy of register transfer level logic of a semiconductor platform description usable by the clock specification, creation and integration tool in accordance with its features. Continue reading about Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit... Full patent description for Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit or other areas of interest. ### Previous Patent Application: Correcting design data for manufacture Next Patent Application: Language and templates for use in the design of semiconductor products Industry Class: Data processing: design and analysis of circuit or semiconductor mask ### FreshPatents.com Support Thank you for viewing the Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit patent info. IP-related news and info Results in 0.2466 seconds Other interesting Feshpatents.com categories: Novartis , Pfizer , Philips , Polaroid , Procter & Gamble , 174 |
 * Protect your Inventions * US Patent Office filing 
PATENT INFO |
|
