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Greg C. Baldwin patents

Recent bibliographic sampling of Greg C. Baldwin patents listed/published in the public domain by the USPTO (USPTO Patent Application #,Title):



10/18/12 - 20120261766 - Compensated isolated p-well denmos devices
An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor...
Inventors: Kamel Benaissa, Greg C. Baldwin, Vineet Mishra, Ananth Kamath (Texas Instruments Incorporated)

10/13/11 - 20110248347 - Low cost transistors using gate orientation and optimized implants
An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or...
Inventors: Kamel Benaissa, Greg C. Baldwin, Shaofeng Yu, Shashank S. Ekbote (Texas Instruments Incorporated)

06/30/11 - 20110156144 - Compensated isolated p-well denmos devices
An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor...
Inventors: Kamel Benaissa, Greg C. Baldwin, Vineet Mishra, Ananth Kamath (Texas Instruments Incorporated)

06/09/11 - 20110133880 - Integrated circuit inductor with integrated vias
Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the...
Inventors: Robert L. Pitts, Greg C. Baldwin (Texas Instruments Incorporated)

12/30/10 - 20100327374 - Low cost transistors using gate orientation and optimized implants
An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or...
Inventors: Kamel Benaissa, Greg C. Baldwin, Shaofeng Yu, Shashank S. Ekbote

12/30/10 - 20100327361 - Low cost symmetric transistors
An integrated circuit is disclosed containing two types of MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or...
Inventors: Kamel Benaissa, Greg C. Baldwin, Shaofeng Yu

12/30/10 - 20100327335 - Method of building compensated isolated p-well devices
Electrical device structures constructed in an isolated p-well that is wholly contained within a core n-well. Methods of forming electrical devices within an isolated p-well that is wholly contained within a core n-well using a baseline CMOS process flow....
Inventors: Kamel Benaissa, Greg C. Baldwin (Texas Instruments Incorporated)

04/16/09 - 20090098694 - Cd gate bias reduction and differential n+ poly doping for cmos circuits
A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of...
Inventors: Shashank Ekbote, Borna Obradovic, Greg C. Baldwin (Texas Instruments Incorporated)

04/16/09 - 20090096031 - Differential poly doping and circuits therefrom
A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and...
Inventors: Shashank Ekbote, Kamel Benaissa, Greg C. Baldwin, Borna Obradovic (Texas Instruments Incorporated)

Texas Instruments Incorporated

Archived*
(*May have duplicates - we are upgrading our archive.)

20110156144 - Compensated isolated p-well denmos devices


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The bibliographic references displayed about Greg C. Baldwin's patents are for a recent sample of Greg C. Baldwin's publicly published patent applications. The inventor/author may have additional bibliographic citations listed at the USPTO.gov. FreshPatents.com is not associated or affiliated in any way with the author/inventor or the United States Patent/Trademark Office but is providing this non-comprehensive sample listing for educational and research purposes using public bibliographic data published and disseminated from the United States Patent/Trademark Office public datafeed. This information is also available for free on the USPTO.gov website. If Greg C. Baldwin filed recent patent applications under another name, spelling or location then those applications could be listed on an alternate page. If no bibliographic references are listed here, it is possible there are no recent filings or there is a technical issue with the listing--in that case, we recommend doing a search on the USPTO.gov website.

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