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Gerard R. Williams, Iii patents

Recent patents with Gerard R. Williams, Iii listed as an inventor - additional entries may be under other spellings.


Gerard R. Williams, Iii - Related organizations: Apple Inc. patents

Marking valid return targets

01/26/17 - 20170024559 - Systems, apparatuses, methods, and computer-readable mediums for preventing return oriented programming (ROP) attacks. A compiler may insert landing pads adjacent to valid return targets in an instruction sequence. When a return instruction is executed, the processor may treat the return as suspicious if the target of the return instruction does
Inventors: Gregory D. Hughes, Conrado Blasco, Gerard R. Williams, Iii, Jacques Anthony Vidrine, Jeffry E. Gonion, Timothy R. Paaske, Tristan F. Schaap

Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture

05/26/16 - 20160147290 - In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance,
Inventors: David J. Williamson, Gerard R. Williams, Iii, James N. Hardage, Jr., Richard F. Russo

Processor including multiple dissimilar processor cores

05/26/16 - 20160147289 - In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, but may have higher minimum voltage at which it operates correctly.
Inventors: David J. Williamson, Gerard R. Williams, Iii

Least recently used mechanism for cache line eviction from a cache memory

02/25/16 - 20160055099 - A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines
Inventors: Brian P. Lilly, Gerard R. Williams, Iii, Mahnaz Sadoughi-yarandi, Perumal R. Subramonium, Hari S. Kannan, Prashant Jain

Branch predictor for wide issue, arbitrarily aligned fetch

02/18/16 - 20160048395 - In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a “fetch group”), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where
Inventors: Ian D. Kountanis, Gerard R. Williams, Iii, James B. Keller

Mechanism for sharing private caches in a soc

05/21/15 - 20150143044 - Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity,
Inventors: Manu Gulati, Harshavardhan Kaushikkar, Gurjeet S. Saund, Wei-han Lien, Gerard R. Williams, Iii, Sukalpa Biswas, Brian P. Lilly, Shinye Shiu

Access map-pattern match based prefetch unit for a processor

01/22/15 - 20150026413 - In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetcher in which patterns may include wild cards for some cache blocks. The wild card may match any access for the corresponding cache block (e.g. no access, demand access, prefetch, successful prefetch, etc.). Furthermore, patterns with irregular strides
Inventors: Stephan G. Meier, Gerard R. Williams, Iii, Hari S. Kannan, Pavlos Konas

Least recently used mechanism for cache line eviction from a cache memory

01/22/15 - 20150026404 - A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines
Inventors: Brian P. Lilly, Gerard R. Williams, Iii, Mahnaz Sadoughi-yarandi, Perumal R. Subramonium, Hari S. Kannan, Prashant Jain

Multi-core processor instruction throttling

10/23/14 - 20140317425 - An apparatus for performing instruction throttling for a multi-processor system is disclosed. The apparatus may include a power estimation circuit, a table, a comparator, and a finite state machine. The power estimation circuit may be configured to receive information on high power instructions issued to a first processor and a
Inventors: Wei-han Lien, Gerard R. Williams, Iii, Rohit Kumar, Sandeep Gupta, Suresh Periyacheri, Shih-chieh R. Wen

Global maintenance command protocol in a cache coherent system

10/23/14 - 20140317358 - A system may include a command queue controller coupled to a number of clusters of cores, where each cluster includes a cache shared amongst the cores. An originating core of one of the clusters may detect a global maintenance command and send the global maintenance command to the command queue
Inventors: Stephan G. Meier, Gerard R. Williams, Iii

It instruction pre-decode

08/28/14 - 20140244976 - Various techniques for processing and pre-decoding branches within an IT instruction block. Instructions are fetched and cached in an instruction cache, and pre-decode bits are generated to indicate the presence of an IT instruction and the likely boundaries of the IT instruction block. If an unconditional branch is detected within
Inventors: Shyam Sundar, Ian D. Kountanis, Conrado Blasco-allue, Gerard R. Williams, Iii, Wei-han Lien, Ramesh B. Gunna

Multi-level dispatch for a superscalar processor

07/31/14 - 20140215188 - In an embodiment, a processor includes a multi-level dispatch circuit configured to supply operations for execution by multiple parallel execution pipelines. The multi-level dispatch circuit may include multiple dispatch buffers, each of which is coupled to multiple reservation stations. Each reservation station may be coupled to a respective execution pipeline
Inventors: John H. Mylius, Gerard R. Williams, Iii, Shyam Sundar Balasubramanian, Conrado Blasco-allue

Persistent relocatable reset vector for processor

07/31/14 - 20140215182 - In an embodiment, an integrated circuit includes at least one processor. The processor may include a reset vector base address register configured to store a reset vector address for the processor. Responsive to a reset, the processor may be configured to capture a reset vector address on an input, updating
Inventors: Josh P. De Cesare, Gerard R. Williams, Iii, Michael J. Smith, Wei-han Lien

Usefulness indication for indirect branch prediction training

07/10/14 - 20140195789 - A circuit for implementing a branch target buffer. The branch target buffer may include a memory that stores a plurality of entries. Each entry may include a tag value, a target value, and a prediction accuracy value. A received index value corresponding to an indirect branch instruction may be used
Inventors: Sandeep Gupta, Shyam Sundar, Wei-han Lien, Gerard R. Williams, Iii, Conrado Blasco-allue

Flush engine

07/10/14 - 20140195737 - Techniques are disclosed related to flushing one or more data caches. In one embodiment an apparatus includes a processing element, a first cache associated with the processing element, and a circuit configured to copy modified data from the first cache to a second cache in response to determining an activity
Inventors: Brian P. Lilly, Gerard R. Williams, Iii

Cache policies for uncacheable memory requests

06/26/14 - 20140181403 - Multiple contiguous store misses are merged into larger blocks of data in the core interface unit before being sent to the L2 cache.
Inventors: Brian P. Lilly, Gerard R. Williams, Iii, Perumal R. Subramoniam, Pradeep Kanapathipillai

Branch predictor for wide issue, arbitrarily aligned fetch

03/27/14 - 20140089647 - In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a “fetch group”), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where
Inventors: Ian D. Kountanis, Gerard R. Williams, Iii, James B. Keller

Multi-destination instruction handling

03/27/14 - 20140089638 - Various techniques for processing instructions that specify multiple destinations. A first portion of a processor pipeline is configured to split a multi-destination instruction into a plurality of single-destination operations. A second portion of the pipeline is configured to process the plurality of single-destination operations. A third portion of the pipeline
Inventors: John H. Mylius, Gerard R. Williams Iii, James B. Keller, Fang Liu, Shyam Sundar

Trust zone support in system on a chip having security enclave processor

03/27/14 - 20140089617 - An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access
Inventors: R. Stephen Polzin, James B. Keller, Gerard R. Williams, Iii

Barrier colors

03/27/14 - 20140089589 - Methods and processors for enforcing an order of memory access requests in the presence of barriers in an out-of-order processor pipeline. A speculative color is assigned to instruction operations in the front-end of the processor pipeline, while the instruction operations are still in order. The instruction operations are placed in
Inventors: Stephan G. Meier, Gerard R. Williams, Iii

Converting memory accesses near barriers into prefetches

01/23/14 - 20140025892 - Methods, apparatuses, and processors for reducing memory latency in the presence of barriers. When a barrier operation is executed, subsequent memory access operations are delayed until the barrier operation retires. While the memory access operation is delayed, the memory access operation is converted into a prefetch request and sent to
Inventors: Gerard R. Williams Iii

Zero cycle load

12/19/13 - 20130339671 - A system and method for reducing the latency of load operations. A register rename unit within a processor determines whether a decoded load instruction is eligible for conversion to a zero-cycle load operation. If so, control logic assigns a physical register identifier associated with a source operand of an older
Inventors: Gerard R. Williams, Iii, John H. Mylius, Conrade Blasco-allue

Load-store dependency predictor pc hashing

12/05/13 - 20130326198 - Methods and processors for managing load-store dependencies in an out-of-order instruction pipeline. A load store dependency predictor includes a table for storing entries for load-store pairs that have been found to be dependent and execute out of order. Each entry in the table includes hashed values to identify load and
Inventors: Stephan G. Meier, John H. Mylius, Gerard R. Williams, Iii, Suparn Vats

Load-store dependency predictor content management

11/07/13 - 20130298127 - Methods and apparatuses for managing load-store dependencies in an out-of-order processor. A load store dependency predictor may include a table for storing entries for load-store pairs that have been found to be dependent and execute out of order. Each entry in the table includes a counter to indicate a strength
Inventors: Stephan G. Meier, John H. Mylius, Gerard R. Williams, Iii, Suparn Vats

Register file power savings

10/31/13 - 20130290681 - A system and method for efficiently reducing the power consumption of register file accesses. A processor is operable to execute instructions with two or more data types, each with an associated size and alignment. Data operands for a first data type use operand sizes equal to an entire width of
Inventors: James B. Keller, John H. Mylius, Conrado Blasco-allue, Gerard R. Williams, Iii, Sandeep Gupta

Optimizing register initialization operations

10/31/13 - 20130290680 - A system and method for efficiently reducing the latency of initializing registers. A register rename unit within a processor determines whether prior to an execution pipeline stage it is known a decoded given instruction writes a particular numerical value in a destination operand. An example is a move immediate instruction
Inventors: James B. Keller, John H. Mylius, Conrado Blasco-allue, Gerard R. Williams, Iii

Zero cycle move

10/17/13 - 20130275720 - A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move
Inventors: James B. Keller, John H. Mylius, Conrado Blasco-allue, Gerard R. Williams, Iii, Suparn Vats

Coordinated prefetching in hierarchically cached processors

09/26/13 - 20130254485 - Processors and methods for coordinating prefetch units at multiple cache levels. A single, unified training mechanism is utilized for training on streams generated by a processor core. Prefetch requests are sent from the core to lower level caches, and a packet is sent with each prefetch request. The packet identifies
Inventors: Hari S. Kannan, Brian P. Lilly, Gerard R. Williams, Iii, Mahnaz Sadoughi-yarandi, Perumal R. Subramoniam, Pradeep Kanapathipillai


### Gerard R. Williams, Iii patent invention listings

The bibliographic references displayed about Gerard R. Williams, Iii's patents are for a recent sample of Gerard R. Williams, Iii's publicly published patent applications. The inventor/author may have additional bibliographic citations listed at the USPTO.gov. FreshPatents.com is not associated or affiliated in any way with the author/inventor or the United States Patent/Trademark Office but is providing this non-comprehensive sample listing for educational and research purposes using public bibliographic data published and disseminated from the United States Patent/Trademark Office public datafeed. This information is also available for free on the USPTO.gov website. If Gerard R. Williams, Iii filed recent patent applications under another name, spelling or location then those applications could be listed on an alternate page. If no bibliographic references are listed here, it is possible there are no recent filings or there is a technical issue with the listing--in that case, we recommend doing a search on the USPTO.gov website.

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