Gain matching for electron multiplication imager

The present invention relates generally to imaging systems, and more particularly to equalization of gain in the output of an array of imaging pixels which employ electron multiplication (impact ionization).

A ubiquitous image sensor technology used in digital cameras is the charge-coupled device (CCD) imager. In a typical CCD imager, signal charge representative of incident radiation is accumulated in an array of pixels in an image area. Following an integration period, the signal charge is transferred to an output register by applying appropriate clocking or drive pulses to control electrodes. The signal charge is then read out from the output register and applied to a charge detection circuit to produce a voltage, which is representative of the amount of signal charge.

It has been found that, with the application of proper gate potentials, a form of gain via impact ionization can be achieved in a CCD device. In a thesis entitled “Avalanche Gain In Charge Coupled Devices,” submitted to the Massachusetts Institute of Technology in August of 1986, Stephanie A. Gagar (hereinafter “Gager”) suggested the incorporation of an impact ionization multiplication of charge in a charge coupled device. Referring now to FIG. 1A, charge 2 is collected and accumulated under a gate 4 in a potential well 6. The accumulated charge 2 is then transferred through an intermediate gate 8 to a storage gate 10 where it is temporarily stored. The original gate 4 wherein the charge was first accumulated is then biased into impact ionization. Referring now to FIG. 1B, charge is then transferred back from the temporary holding gate 10 to the accumulating gate 4 which is now biased as an impact ionization gate. This is accomplished by pulsing the holding gate 10 to a lower potential and transferring the charge through the intermediate gate 8 to the impact ionization region. For further gain, this procedure is repeated multiple times, i.e. 100 to 500 times, to build up charge. The gain per impact ionization transfer is roughly 1.015×. The gain after N impact ionization transfers is roughly (1.015)^N. For N equal to 400, the resulting gain is about 386. Once sufficient charge has been built up, the charge is moved off of the CCD gates to a charge sensitive amplifier for charge-to-voltage conversion and read out.

A second design employing impact ionization can be found in pending commonly owned U.S. application Ser. No. 11/863,945 filed Sep. 28, 2007 to John Robertson Tower et al. (hereinafter “Tower et al.”), which is incorporated herein by reference in its entirety. Referring now to FIGS. 2A and 2B, plan views of the Tower et al. EMCMOS device layout and architecture are depicted. Charge collection, storage, and electron multiplication (EM) regions are incorporated into a single pixel 30 formed monolithically as an integrated circuit. The pixel 30 includes electron multiplication (EM) gain regions 32, 34 whose accumulated charge circulates around an enclosed track or circulating register called the EM gain register 36. In FIGS. 2A, 2B, there are a total of eight gates which constitute two stages of the EM gain register 36: PHI (clocked gate) 38, DC gate 40, EM (high voltage clocked gate) 42, DC gate 44, PHI 46, DC Gate 48, EM 50, and DC Gate 52. In the more general case, the Tower et al. device can comprise one or more impact ionization gain stages with implants to achieve charge transfer directionality.

A readout structure 54 comprising a number of sub-structures are fabricated in the pixel 30 nested within the EM gain register 36. The light sensitive area, which creates electrons in proportion to the radiant energy incident on the pixel 30 can be an optical-to-charge conversion device such as a pinned photodiode (PPD) 56 as shown, a photogate, etc. The PPD 56 is connected to and releases the accumulated charge to the EM gain register 36 by means of a PPD transfer gate (TR1) 58. A floating diffusion sense node 60 for receiving amplified charge from the EM gain register 36 and for converting the charge to a voltage is also connected to the EM gain register 36 by means of a floating diffusion transfer gate (TR2) 62. The readout circuitry 54 includes a row select gate 64, a PPD reset gate 66, a source follower transistor 68, and a source follower reset gate 70. Power is supplied to the pixel 30 by means of power rail VDD 72. The pixels 30 can be manufactured using a CMOS process, preferably a PPD CMOS process.

Referring now to FIGS. 3A-3C, a schematic cross-section of one stage (4 gates) of the (EM) gain register 36 and accompanying applied potential diagrams of the pixel 30 is depicted. Each EM gain stage includes four gates: a first DC gate 74, a phase 1 clock gate 76, a second DC gate 78, and a phase 2 clock gate 80 which is employed to control the electron multiplication function. The clocking of the EM gain register 36 is done with two clock phases, as shown in FIG. 4A. During a first clock period shown in FIG. 3B, the phase 1 clock gate 76 has a first potential applied to it to hold the accumulate charge (electrons) in a charge packet 82 in a potential well 84 below the phase 1 clock gate 76. Meanwhile, a larger potential is applied to the phase 2 clock gate 80 to create a potential well 86, which is initially devoid of charge. Barrier regions 88, 90 are created below the DC gates 74, 78, respectively, to assure proper direction of charge transfer between the clock gates 76, 80 and between the (EM) gain regions 32, 34 by the application of appropriate low DC voltage levels relative to the high voltages applied to the clock gates 76, 80 when they are in their high (on) state. During a second clock cycle shown in FIG. 3C, the potential of the phase 1 clock gate 76 is changed to about 0 volts which is lower than the potential applied to the DC gates 74, 78. Electrons that have accumulated below the phase 1 gate clock 76 now “spill” over into the well 86 and can undergo impact ionization at the interface 94 between the second DC gate 78 and the phase 2 clock gate 80. As a result, the electron charge packet 82 transfers to the well 86. Proper directionality is achieved by optimized implants.

The electrons in a charge packet 82 are made to circulate a predetermined number of times through the EM gain regions 32, 34 in the pixel 30. Although the probability of impact ionization, and thus the mean gain per stage g for each of the EM gain regions 32, 34 is low, the number of times that the charge packet 82 pass around the EM gain registers 36 and through EM gain regions 32, 34 in the pixel 30, designated as N, can be high. The total gain of the cascaded multiplication elements (EM gain regions 32, 34) is given by M=g^N. For N=600 and g=1.015 (1.5 percent probability of impact ionization), the total gain in the charge domain is over 7500×.

FIGS. 4A-4D illustrate the operation of the pixel 30 of FIGS. 2A and 2B. In a first time period (FIG. 4A), a charge packet 82 accumulated in the pinned photodiode (PPD) 56 is loaded into the EM gain register 36 via the PPD transfer gate 58 (TR1). In a second time period (FIG. 4B), the charge packet 82 circulates around the EM gain register 36 through the EM gain regions 32, 34. As a result, the charge packet 82 circulating around EM gain register 36 accumulates nominally about 400 transfers through the EM gain regions 32, 34 (200 cycles). In a third time period (FIG. 4C), the amplified charge packet 82 is transferred to the floating diffusion sense node 60 by means of the floating diffusion transfer gate 62 where the charge packet is converted to a voltage, the floating diffusion sense node 60 acting like a capacitor. In a fourth time period (FIG. 4D), the floating diffusion sense node 60 and the PPD 56 are reset (global reset) via the PPD reset gate 66. Then the sequence is repeated for the next frame.

For both the “linear” architecture of the Gager device and the “circular” architecture of the Tower et al. device, as well as other CCD or CMOS pixels employing impact ionization in the prior art, if the pixels are arranged in a two dimensional array, a problem arises in that, since each pixel has slightly different design and process tolerances, the electron multiplication gain may differ from pixel to pixel. Although slight differences of device parameters may have little effect on the signal charge and output voltage for a single pass through EM gain regions, differences in gain are magnified as a result of charge circulating through the EM gain regions hundreds of times.

Accordingly, what would be desirable, but has not yet been provided, is a means of equalizing gain among solid state EM gain pixels arranged in arrays.