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Fluorine-modification process and applications thereof

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Fluorine-modification process and applications thereof


The present invention is related to a process for reducing surface energy of a hole transport layer. The disclosed process comprises providing a hole transport layer; and providing a fluorine-containing layer directly on said hole transport layer. The configuration of said fluorine-containing layer reduces the structural disorder of an active layer and is able to recover a moisture-degraded hole transport layer, and thereby improves the performance of an electric device containing the same.
Related Terms: Transport Layer

Browse recent Academia Sinica patents - Taipei, TW
USPTO Applicaton #: #20130328018 - Class: 257 40 (USPTO) - 12/12/13 - Class 257 
Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Organic Semiconductor Material

Inventors: Kuei-hsien Chen, Hsieh-cheng Han, Ching-chun Chang, Li-chyong Chen, Chan-yi Du

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The Patent Description & Claims data below is from USPTO Patent Application 20130328018, Fluorine-modification process and applications thereof.

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FIELD OF THE INVENTION

The present invention is related to the improvement of power conversion efficiency for an electronic device; more specifically to the improvement of power conversion efficiency for an organic solar cell.

DESCRIPTION OF THE PRIOR ART

Organic solar cells (OSC) have attracted much attention during the recent decades. Compared to the conventional photovoltaic devices, the organic solar cells have advantageous in low-cost fabrication and flexibility.

In an organic solar cell, excitons are generated by photoexcitation of an organic solid. The active materials at OSC, in their corresponding donor/acceptor phases, provide the driving force for the exciton dissociation into charge carriers at the interfaces. The two phases must form bi-continuous networks for efficient excitons diffusion and charge separation. The recombination of charge carriers can also hinder the separation process and hence reduce the power conversion efficiency (PCE). Literatures have shown that the lower molecular doping could reduce the interfacial recombination and improve the OSCs performances greatly. The structure order or dipoles at the interface would also enhance the charge-separation rate.

The separated charge carriers will be transported efficiently through the donor and acceptor layers and collected by the corresponding electrodes. It had been reported that the PCE of the devices with a highly ordered bulk hetero-interface could be largely increased by high carrier-transport efficiency. Selective control of doping and band-edge energies with minimal mid-gap states could optimize the carrier transporting and collecting efficiencies. Besides, the modifications out for both contacts, balancing the rates of hole and electron collection, could elevate the overall efficiencies.

Interface engineering between the anode and the active layer is important for the device lifetime as well as power conversion efficiency in solar cells. For instance, hole-injecting conducting polymer films such as poly(3,4-ethylenedioxythiophene) (PEDOT) on indium tin oxide (ITO) play important roles in determining the device efficiency and stability, because of improving in carrier transporting properties at the ITO/active materials interfaces and also the planarization of the ITO surface.

On the other hand, it is known that the morphology of the P-layer of an active layer in an OSC structure also has significant impact on the performance thereof. In a pentacene-based OSC, the general morphology of pentacene thin film is comprised by mixed crystalline domains (grains) with dendritic structures and isolated fiber-like features. The coexistence of the long-axis oriented dendrite-like domains (perpendicular to the substrate) and the fiber-like structures lying flat on the substrate leads to high degree of structural disorder. Such structural disorder has been reported for degrading the electrical performances of devices, attributed to the trap states existed at the grain boundaries.

Moreover, the device lifetime is an important issue for OSC applications. The degradation of device performance may be caused by the absorbed moisture during the manufacture and/or the operation of the OSC. Therefore, during the manufacture process, the configuration or deposition of elements of an OSC, especially a hole transport layer (ex. a PEDOT:PSS layer), is generally necessary to be conducted in a glove box with a limited moisture. Besides, some may configure water absorbing agents inside the package of an OSC to prevent moisture in the OSC structure, and thereby to prolong the lifetime thereof. However, to operate the manufacture process in a glove box not only raises the manufacturing cost but also hinders mass production for commercialization of OSC. In addition, configuring water absorbing agents may also result in additional manufacture cost.

To sum up, there are several factors/problems known to be important to the performance and commercialization of OSCs; however, those factors/problems still need to be clarified or solved. Therefore, an OSC with better power conversion efficiency is continued required in this filed.

SUMMARY

OF THE INVENTION

In view of the foregoing, one object of the present invention is to increase the power conversion efficiency of an OSC by decreasing the structural disorder of the active layer thereof.

Another object of the present invention is to improve the long term stability of an OSC by decreasing the absorbed moisture in the OSC structure.

To achieve the above objects, the present invention provides a process for reducing surface energy of a hole transport layer, comprising the following steps: providing a hole transport layer; and providing a fluorine-containing layer directly on said hole transport layer.

The present invention also provides a process for recovering a moisture-degraded hole transport layer, comprising the following steps: obtaining a moisture-degraded hole transport layer; and providing a fluorine-containing layer directly on said moisture-degraded hole transport layer.

The present invention also provides a process for manufacturing an electronic device, comprising the following steps: providing a substrate coated with a conductive material as a cathode; providing a hole transport layer on said substrate; providing a fluorine-containing layer directly on said hole transport layer; providing an active layer directly on said fluorine-containing layer; providing an electron transport layer on said active layer; and providing an anode on said electron transport layer.

The present invention further provides an electronic device, comprising electric-connected layers in order: a cathode; a hole transport layer; a fluorine-containing layer, which is deposited directly on said hole transport layer; an active layer, which is deposited directly on said fluorine-containing layer, an electron transport layer; and an anode.

Preferably, said providing said fluorine-containing layer comprising the following steps: obtaining a liquid by dissolving a fluorine-containing material in a solvent; and depositing said liquid on said hole transport layer.

Preferably, said liquid comprises: 0.01-10 volume percentage concentration of said fluorine-containing material; wherein said volume percentage concentration is based on the total volume of said solvent.

Preferably, said solvent comprises chlorobenzene, ethanol, water, or a mixture thereof.

Preferably, said fluorine-containing material comprises fluorocarbon, silane derives thereof, or a mixture thereof.

Preferably, said silane derives of fluorocarbon comprises polyfluoroalkoxysilane.

Preferably, said polyfluoroalkoxysilane comprises (heptadecafluoro-1,1,2,2-tetra-hydrodecyl) trimethoxysilane, and a mixture thereof.

Preferably, said fluorocarbon comprises perfluorononane.

Preferably, said process for reducing surface energy of a hole transport layer , said process for recovering a moisture-degraded hole transport layer and/or said process for manufacturing an electronic device further comprises a heating step of heating said fluorine-containing layer at a temperature of 50˜300° C.

Preferably, said heating step is conducted by thermal treatment, microwave treatment, or a combination thereof.

Preferably, said hole transport layer and/or said moisture-degraded hole transport layer comprises polyethylenedioxythiophene, polystyrenesulfonate, polyaniline, polyphenylenevinylene, TPD, NPB, or a mixture thereof. More preferably, said hole transport layer and/or said moisture-degraded hole transport layer is a polyethylenedioxythiophene: polystyrenesulfonate layer (a PEDOT:PSS layer).

Preferably, said process for reducing surface energy of a hole transport layer , said process for recovering a moisture-degraded hole transport layer and/or said process for manufacturing an electronic device is conducted at atmosphere.



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stats Patent Info
Application #
US 20130328018 A1
Publish Date
12/12/2013
Document #
13494888
File Date
06/12/2012
USPTO Class
257 40
Other USPTO Classes
438 99, 257E51031
International Class
/
Drawings
8


Transport Layer


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