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Floorplanning a hierarchical physical design to improve placement and routingRelated Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, FloorplanningFloorplanning a hierarchical physical design to improve placement and routing description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070136709, Floorplanning a hierarchical physical design to improve placement and routing. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATION [0001] This patent application claims the benefit of copending U.S. Provisional Patent Application, Ser. No. 60/465115, filed Apr. 23, 2003, entitled "ADVANCED BLOCK FLOORPLANNING IN ABUTTED HIERARCHICAL CHIP DESIGN," by Paul Rodman. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention generally relates to floorplanning a physical design for an integrated circuit chip. More particularly, the present invention relates to the field of floorplanning a hierarchical physical design to improve placement and routing. [0004] 2. Related Art [0005] The process of generating a physical design for an integrated circuit chip is complicated. The physical design represents the layout of the integrated circuit chip on a semiconductor, such as silicon, and is utilized to fabricate the integrated circuit chip. There are several types of physical designs: flat physical designs and hierarchical physical designs. Typically, the physical design is generated in several stages. Examples of these stages include floorplanning, placement, routing, and verification. In a flat physical design these stages are sequentially performed on the entire layout, while in a hierarchical physical design these stages are sequentially performed on partitions of the layout referred as blocks (or place-and-route blocks). [0006] Floorplanning is performed before placement and routing. Thus, floorplanning affects subsequent stages such as placement and routing. The main goal and objective of floorplanning is creating a floorplan. The floorplan can determine whether placement and routing are possible for the physical design. [0007] During the top-level floorplanning stage of a hierarchical physical design, blocks are arranged on a selected chip area and chip shape. In arranging the blocks, individual blocks are sized and shaped. These blocks can have any number of cells that execute digital or analog functions (e.g., NAND, NOR, D flip-flop, etc.) by connectively grouping circuit elements such as transistors, capacitors, resistors, and other circuit elements. Moreover, these blocks can have one or more macrocells. A macrocell is a functional module such as RAM, ROM, ALU, etc. Each of these cells and macrocells has one or more ports (or terminals) for inputting signals or outputting signals, each of which, in turn, may connect to one or more ports of other cells and macrocells via metal wires. A net is a set of two or more ports that are connected. Generally, the input to the floorplanning stage is a netlist for the integrated circuit chip. A netlist is a list of nets for the integrated circuit chip. [0008] Continuing, the location of Input/Output blocks is determined. These Input/Output blocks facilitate connections/communication with external components. An Input/Output block may have bonding pad cells or bump cells. Moreover, power distribution and clock distribution are determined during the top-level floorplanning stage of the hierarchical physical design. Furthermore, the top-level floorplanning stage is performed with the objectives of minimizing the chip area and minimizing delay. SUMMARY OF THE INVENTION [0009] Methods for floorplanning a hierarchical physical design to improve placement and routing are provided and described. In one embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. Each block includes a plurality of linear edges. Additionally, at least one of the blocks is selected. Furthermore, at least one linear edge of the selected block is rasterized. This rasterization includes converting the linear edge to a stepped-shape edge. [0010] In another embodiment, a method of floorplanning a hierarchical physical design includes performing an initial flat placement using a netlist of the hierarchical physical design. Continuing, a plurality of partitions of the netlist in the initial flat placement are identified, wherein each partition has a boundary. Moreover, a top-level floorplan for the hierarchical physical design is generated using the initial flat placement. In generating the top-level floorplan, a corresponding block for each identified partition is generated by converting the boundary of the identified partition into a plurality of edges. The plurality of edges includes at least one stepped-shape edge. [0011] In yet another embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. An area unoccupied by the blocks and surrounding at least one of the blocks is selected. Moreover, the area is designated as an additional block, wherein the additional block has a gap where the surrounded block is located. [0012] In still another embodiment, a method of floorplanning a physical design includes assigning a priority attribute to each one of a plurality of blocks. Each priority attribute determines which block owns any overlap area relative to another block. Continuing, the blocks are arranged to form one or more overlap areas. Each overlap area is allocated to one of the blocks based on the assigned priority attribute of the blocks. [0013] In another embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. Moreover, a plurality of nets is routed in the top-level of the hierarchical physical design to determine pin locations for each block. Each pin of each block represents one of a location where a signal enters the block and a location where a signal exits the block. Continuing, it is determined whether a routed net includes a plurality of segments within a block. Furthermore, one or more of the segments are renamed. BRIEF DESCRIPTION OF THE DRAWINGS [0014] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the present invention. [0015] FIG. 1A illustrates a top-level floorplan of an abutted-pin hierarchical physical design in accordance with an embodiment of the present invention. [0016] FIG. 1B illustrates the two-level hierarchy of the abutted-pin hierarchical physical design of FIG. 1A in accordance with an embodiment of the present invention. [0017] FIG. 2 illustrates a first top-level floorplan of the core area of a hierarchical physical design in accordance with an embodiment of the present invention. [0018] FIG. 3A illustrates a second top-level floorplan of the core area of a hierarchical physical design in accordance with an embodiment of the present invention. [0019] FIG. 3B illustrates a third top-level floorplan of the core area of a hierarchical physical design in accordance with an embodiment of the present invention. [0020] FIG. 4A illustrates a first top-level floorplan showing rasterization in the core area of a hierarchical physical design in accordance with an embodiment of the present invention. Continue reading about Floorplanning a hierarchical physical design to improve placement and routing... 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