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Flexible scan architectureRelated Patent Categories: Error Detection/correction And Fault Detection/recovery, Pulse Or Data Error Handling, Skew Detection CorrectionFlexible scan architecture description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070168767, Flexible scan architecture. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD [0001] The present application is a continuation application of and claims the priority date of U.S. patent application Ser. No. 10/609,254 entitled "FLEXIBLE SCAN ARCHITECTURE," filed Jun. 26, 2003 and assigned to the assignee of the present invention. [0002] Embodiments of the invention relate to microprocessor testing architecture. More particularly, embodiments of the invention relate to a flexible scan architecture that enables isolation of various portions of a microprocessor for testing purposes independently of their functional mode. BACKGROUND [0003] As microprocessor architecture complexity and gate-count increases, so does the complexity and necessity of having adequate test coverage of each functional unit. Furthermore, increases in test coverage typically brings increased test time, power, and other effects that can increase the cost of testing. [0004] Prior art testing architectures typically group functional units into testing groups, such as clusters and sub-cluster units, such that they are tested at once, thereby decreasing the amount of die real estate necessary to accommodate the testing circuitry. This technique, however, is often at the expense of comprehensive test coverage, as the functional units within the testing groups cannot be isolated and independently tested. [0005] Prior art testing architectures also typically control the testing architecture logic with the same clock (or some derivative thereof) as the functional or system clock of the processor, thereby introducing delay and other timing problems into the testing of the processor, reducing the overall test time. [0006] Finally, some prior art techniques typically separate various hierarchical testing groups in the testing architecture using logic that precludes one set of functional units from being tested with an automatic test pattern while another set of functional units are being operated under normal processor operating conditions. Such a testing architecture can be limiting in that it forces one to make trade-offs between test coverage, test time, and power concerns. BRIEF DESCRIPTION OF THE DRAWINGS [0007] Embodiments of the invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which: [0008] FIG. 1 illustrates computer system in which a processor may be used containing at least one embodiment of the invention. [0009] FIG. 2 illustrates a processor architecture in which at least one embodiment of the invention may be used. [0010] FIG. 3 illustrates a test scan model according to one embodiment of the invention. [0011] FIG. 4 illustrates control blocks for a test scan architecture according to one embodiment of the invention. [0012] FIG. 5 illustrates a scan chain architecture used in a test scan architecture according to one embodiment of the invention. [0013] FIG. 6 illustrates a scan chain configuration for supporting a partitioned-based automatic test pattern generator according to one embodiment of the invention. [0014] FIG. 7 illustrates a functional control architecture for supporting a partitioned-based automatic test pattern generator according to one embodiment of the invention. [0015] FIG. 8 illustrates a scan clock control architecture for supporting a partitioned-based automatic test pattern generator according to one embodiment of the invention. [0016] FIG. 9 illustrates a local test control circuit used in conjunction with at least one embodiment of the invention. DETAILED DESCRIPTION [0017] Embodiments of the invention relate to microprocessor testing architecture. More particularly, embodiments of the invention relate to a flexible scan architecture that enables isolation of various portions of a microprocessor for testing purposes independently of their functional mode. [0018] Embodiments of the invention described herein enable the isolation and independent testing of functional units throughout a processor architecture by using a scan clock chain architecture that is separate and independent of the processor's functional, or system, clock chain structure. Furthermore, embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects. [0019] FIG. 1 illustrates a computer system in which at least a portion of one embodiment of the invention may be performed. A processor 105 accesses data from a cache memory 110 and main memory 115, which comprises a memory system. [0020] Illustrated throughout the processor of FIG. 1 is logic 106 for controlling a test scan architecture according to one embodiment of the invention. The particular configuration of the test architecture logic illustrated in FIG. 1 may be different in other embodiments. Furthermore, embodiments of the invention may be implemented within other devices within the system, such as a separate bus agent, or distributed throughout the system in hardware, software, or some combination thereof. Continue reading about Flexible scan architecture... Full patent description for Flexible scan architecture Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Flexible scan architecture patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Flexible scan architecture or other areas of interest. ### Previous Patent Application: System and method for auxiliary channel error messaging Next Patent Application: Providing precise timing control between multiple standardized test instrumentation chassis Industry Class: Error detection/correction and fault detection/recovery ### FreshPatents.com Support Thank you for viewing the Flexible scan architecture patent info. IP-related news and info Results in 0.12189 seconds Other interesting Feshpatents.com categories: Software: Finance , AI , Databases , Development , Document , Navigation , Error 174 |
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