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Fin field effect transistor and method for manufacturing fin field effect transistorRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect DeviceFin field effect transistor and method for manufacturing fin field effect transistor description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070126032, Fin field effect transistor and method for manufacturing fin field effect transistor. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of Invention [0002] The present invention relates to a fin field effect transistors (FinFETs) and a method for manufacturing the FinFETs. More particularly, the present invention relates to a FinFET with a fully silicidated gate electrode and a method for manufacturing thereof [0003] 2. Description of Related Art [0004] FinFETs have been demostrated to have better scalibility than traditional bulk transistors. Generally, the operations of digital circuit depend on the ability to switch MOS devices from an ON state to an OFF state and vice versa. If the threshold voltage for N-type MOS is not much difference from that for P-type MOS even the margin of the ON and OFF state of the N-type MOS seriously overlap with that of the P-type MOS under general operating current, the circuit will be malfutnction under specific operating voltage range. [0005] FIG. 1 shows the Id-Vg (drain current versus gate voltage) plots for the conventional FinFETs. It is well known in the art that while a positive voltage, which is higher than the threshold voltage of the N-type MOS, is applied on the gate of the N-type MOS, an N-channel is formed under the gate and between the source and drain, and then the N-type MOS is turned on under a proper bias. Similarly, while a negative voltage, which is lower than the threshold voltage of the P-type MOS, is applied on the gate of the P-type MOS, a P-channel is formed under the gate and between the source and drain, and then the P-type MOS is turned on under a proper bias. However, as shown in FIG. 1, while a positive voltage of about 0.25V is applied on the gate, not only the N-type MOS is turned on, but also there is current of about 10.sup.-7 Amp passing through the drain of the P-type MOS. That is, the P-type MOS is also turned on. Similarly, while a negative voltage of about -0.25V is applied on the gate, the P-type MOS is turned on and the N-type MOS is turned on as well. Therefore, it is easily to induce circuit malfinction under this kind of circumstance. Even while the drain current is about of 10.sup.-6, which is a general drain current under the normal circuit operation, it is also possible to turn on the P-type MOS and the N-type MOS at the same gate voltage. SUMMARY OF THE INVENTION [0006] The invention provides a method for manufacturing a fin field effect transistor having a fully silicidated gate electrode. The method is suitable for a substrate having a fin structure, a straddle gate and a source/drain region formed thereon, wherein the straddle gate straddles over the fm structure and the source/drain region is located in a portion of the fin structure exposed by the straddle gate. The method comprises steps of performing a first salicide process to form a first salicide layer on the top of the straddle gate and a second salicide layer on the source/drain region. A dielectric layer is formed over the wafer and then a planarization process is performed to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed. Moreover, a second salicide process is performed to convert the straddle gate into a fully silicidated gate electrode. [0007] The present invention further provides a fin field effect transistor having a fully silicidated gate electrode suitable for a substrate having a fin structure formed thereon. The fin field effect transistors comprises a fully silicidated gate electrode, a source/drain region and a salicide layer. The fully silicidated gate electrode straddles over a portion of the fin structure and the source/drain region is located in the fin structure exposed by the fully silicidated gate electrode and adjacent to the fully silicidated gate electrode. In addition, the salicide layer is located on the source/drain region. [0008] Because the straddle gate of the fin field effect transistor is fully silicidated into a fully silicidated gate electrode, the result workfunction of the fin field effect transistor is properly adjusted so that the margin of ON/OFF voltage of the N-type MOS is apparently distinguished from that of the P-type MOS. Therefore, the device having N-type and P-type FinFETs formed by the method according to the present invention possesses relatively better functionality and performance. Hence, the malfunction problem caused by simultaneously turn on both N-type and P-type FinFETs can be overcome. [0009] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. BRIEF DESCRPTOIN OF THE DRAWINGS [0010] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. [0011] FIG. 1 shows the Id-Vg (drain current versus gate voltage) plots for the conventional FinFETs. [0012] FIGS. 2-3 and 5-10 are perspective views showing the steps for manufacturing FinFETs according to one preferred embodiment of the present invention. [0013] FIG. 4 is a 3-D schema of a FinFET. [0014] FIG. 4A is a cross-sectional view along line I-I of FIG. 4. [0015] FIG. 4B is a cross-sectional view along line II-II of FIG. 4. [0016] FIG. 11 shows the Id-Vg (drain current versus gate voltage) plots for the FinFETs according to one embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS [0017] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. [0018] As shown in FIG. 2, an initial structure is provided for fabricating FinFETs according to one embodiment of the present invention. The initial structure shown in FIG. 2 is divided into a region 200a and a region 200b and comprises a substrate 202, an insulating layer 204 and a plurality of fin structures. Moreover, in the region 200a, the fin structure comprises a top cap layer 208 and a raised fin 206a with a first conductive type. Similarly, in the region 200b, the fin structure comprises a top cap layer 208 and a raised fin 206b with a second conductive type. Notably, the first conductive type and the second conductive type can be, for example but not limited to, P type and N type, respectively. The method for forming the initial structure comprises the steps of providing a silicon-on-insulating (SOI) material (not shown) including, for example, a bottom Si-containing layer (substrate 202), the insulating layer 204 and a top Si-containing layer (not shown). Then, a pattern process is performed to form the fin structures after a dielectric layer (not shown) is formed over the SOI material. The insulating layer 204, such as buried oxide layer, electrically isolates the bottom Si-containing layer from the top Si-containing layer. The Si-containing layer can be semiconductor material including at least silicon. The semiconductor material can be, example but not limited to, silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), polysilicon, epitaxial silicon, amorphous silicon and multi-layers formed thereof. Further, the dielectric layer can be, for example, a nitrided thermal oxide layer. Moreover, the pattern process for forming the fin structure comprises the steps of forming a patterned phtoresist layer (not shown) over the SOI material and then patterning the dielectric layer and the SOt material until the surface of the insulating layer 204 is exposed to form the raised-undoped fm and the cap layer 208. Then, a patterned photoresist layer (not shown) is formed over the region 200b to expose the region 200a. Thereafter, an ion implantation process is performed to implant ions with the first conductive type into the raised-undoped fin in the region 200a and the rased-undoped fin in region 200a is transformed into the fin 206a. The ions for forming fin 206a can be, for example but not limited to, boron ions. Then the patterned photoresist layer is removed. After, a patterned photoresist layer (not shown) is formed over the region 200a to expose the region 200b. Thereafter, an ion implantation process is performed to implant ions with the second conductive type into the raised-undoped fin in the region 200b and the rased-undoped fin in region 200b is transformed into the fin 206b. The ions for forming fin 206b can be, for example but not limited to, phosphorous ions. Then, the patterned photoresist layer is removed. Before the steps for forming the fin 206a and the fin 206b, it can comprises, for example, a step of forming a sacrificial oxide layer (not shown) on the sidewall of the raised fin to protect the raised-undoped fin from being damaged by subsequent performed implantation process. Thereafter, a gate material layer 210 is formed over the region 200a and the region 200b. The gate material layer 210 can be, for example but not limited to, an undoped polysilicon layer. [0019] As shown in FIG. 3, a patterned photoresist layer (not shown) is formed over the region 200b to expose the region 200a. An ion implantation process is performed to implant ions with the second conductive type into a portion of the gate material layer 210 in the region 200a and transform the portion of the gate material layer 210 into a doped gate material layer 210a. The ions used in the ion implantation process can be, for example, phosphorous ions. Next, the patterned photoresist layer is removed. After the ion implantation process is performed, it further comprises, for example, a step of annealing process. The annealing process can be, for example, a rapid thermal process performing at temperature of about 850 centigrade for about 20 seconds. [0020] A pattern process is performed to pattern the gate material layer 210a in region 200a and the gate material layer 210 in the region 200b to form a straddle gates 212a and 212b, respectively. FIG. 4 is a 3-D schema of one of FinFETs comprising the straddle gate 212a/212b and the fin 206a/206b after the pattern process is performed. FIG. 4A is a cross-sectional view along line I-I of FIG. 4. FIG. 4B is a cross-sectional view along line II-II of FIG. 4. Continue reading about Fin field effect transistor and method for manufacturing fin field effect transistor... Full patent description for Fin field effect transistor and method for manufacturing fin field effect transistor Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Fin field effect transistor and method for manufacturing fin field effect transistor patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Fin field effect transistor and method for manufacturing fin field effect transistor or other areas of interest. ### Previous Patent Application: Semiconductor device and method for manufacturing same, and semiconductor wafer Next Patent Application: Semiconductor integrated circuit and method of manufacturing the same Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the Fin field effect transistor and method for manufacturing fin field effect transistor patent info. IP-related news and info Results in 0.63639 seconds Other interesting Feshpatents.com categories: Electronics: Semiconductor , Audio , Illumination , Connectors , Crypto , 174 |
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