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Field emission-type electron source and method of producing the sameRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Thin Active Physical Layer Which Is (1) An Active Potential Well Layer Thin Enough To Establish Discrete Quantum Energy Levels Or (2) An Active Barrier Layer Thin Enough To Permit Quantum Mechanical Tunneling Or (3) An Active Layer Thin Enough To Permit Carrier Transmission With Substantially No Scattering (e.g., Superlattice Quantum Well, Or Ballistic Transport Device), Low Workfunction Layer For Electron Emission (e.g., Photocathode Electron Emissive Layer)Field emission-type electron source and method of producing the same description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060049393, Field emission-type electron source and method of producing the same. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] The present invention relates to a field emission-type electron source for emitting electron beams by means of the field emission phenomenon, and a method of producing such a field emission-type electron source. BACKGROUND ART [0002] As one type of electron devices utilizing nanocrystalline silicon (nano-order silicon nanocrystal), there has heretofore been known a field emission-type electron source as shown in FIGS. 17 and 18 (see, for example, Japanese Patent Publication Nos. 2987140 and 3112456). [0003] The field emission-type electron source 10' (hereinafter referred to as "electron source" for brevity) illustrated in FIG. 17 includes an n-type silicon substrate 1 as a conductive substrate, a strong-field drift layer (hereinafter referred to as "drift layer" for brevity) 6 composed of an oxidized porous silicon layer and formed on the side of a main surface of the n-type silicon substrate 1, a surface electrode 7 composed of a metal thin film (e.g. gold thin film) and formed on the front surface of the drift layer 6, and an ohmic electrode 2 formed on the back surface of the n-type silicon substrate 1. The combination of the n-type silicon substrate 1 and the ohmic electrode 2 serves as a lower electrode 12. In the electron source 10' illustrated in FIG. 17, a non-doped polycrystalline silicon layer 3 is interposed between the n-type silicon substrate 1 and the drift layer 6 to make up an electron transit section in combination with the drift layer 6. In this connection, there has also been known another electron source having an electron transit section composed only of the drift layer 6 without any polycrystalline silicon layer 3 interposed between the n-type silicon substrate 1 and the drift layer 6. [0004] The electron source 10' illustrated in FIG. 17 is operable to emit electrons, for example, according to the following process. A collector electrode 21 is first arranged at a position opposed to the surface electrode 7. The space formed between the surface electrode 7 and the collector electrode 21 is kept in vacuum. Then, a DC voltage Vps is applied between the surface electrode 7 and the lower electrode 12 in such a manner that the surface electrode 7 has a higher potential than that of the lower electrode 12. Simultaneously, a DC voltage Vc is applied between the collector electrode 21 and the surface electrode 7 in such a manner that the collector electrode 21 has a higher potential than that of the surface electrode 7. The DC voltage Vps can be set at an appropriate value to allow electrons injected from the lower electrode 12 into the drift layer 6 to drift around the drift layer 6 and then run out through the surface electrode 7 (one-dot chain lines in FIG. 17 indicate the flows of the electrons e.sup.- emitted through the surface electrode 7). The thickness of the surface electrode 7 is set in the range of about 10 to 15 nm. [0005] While the lower electrode 12 in the electron source 10' illustrated in FIG. 17 is composed of the n-type silicon substrate 1 and the ohmic electrode 2, it may be substituted with a combination of an insulative substrate 11 composed of a glass substrate having an insulation performance, and a metal thin film formed on one of the surfaces of the insulative substrate 11, as in another conventional electron source 10'' illustrated FIG. 18. In FIG. 18, the same component or element as that of the electron source 10' illustrated in FIG. 17 is defined by the same reference numeral or code. The electron source 10'' is operable to emit electrons according to the same process as that in the electron source 10' illustrated in FIG. 17. Electrons getting through to the front surface of the drift layer 6 are considered to be hot electrons. Thus, such electrons can readily tunnels through the surface electrode 7 and run out into the vacuum space. [0006] Generally, in the electron sources 10' , 10'', a current flowing between the surface electrode 7 and the lower electrode 12 is termed as "diode current Ips", and a current flowing between the collector electrode 21 and the surface electrode 7 is termed as "emission current (emission electron current) Ie". An electron emission efficiency [(Ie/Ips).times.100(%)] in the electron sources 10' , 10'' is enhanced as the ratio (Ie/Ips) of the emission current Ie to the diode current is increased. Each of the electron sources 10' , 10'' is operable to emit electrons even if the DC voltage Vps to be applied between the surface electrode 7 and the lower electrode 12 is set at a low value in the range of about 10 to 20 V. The emission current Ie is increased as the DC voltage Vps is set at a higher value. [0007] The electron source 10'' illustrated in FIG. 18 is produced, for example, by the following steps. As shown in FIG. 19A, a lower electrode 12 is first formed on one main surface (hereinafter referred to as "front surface") of the insulative substrate 11 through a sputtering process or any other suitable process. Subsequently, a non-doped polycrystalline silicon layer 3 is formed on the front surface of the lower electrode 12 through a plasma CVD process or any other suitable process, at a substrate temperature of 400.degree. C. or more. [0008] Then, as shown in FIG. 19B, the polycrystalline silicon layer 3 is anodized up to a given depth thereof to form a porous polycrystalline silicon layer 4'. The porous polycrystalline silicon layer 4' includes a plurality of polycrystalline silicon grains, and a number of nanometer-order silicon nanocrystals. Subsequently, as shown in FIG. 19C, the porous polycrystalline silicon layer 4' is oxidized through a rapid heating process or an electrochemical oxidation process to form a drift layer 6. Then, as shown in FIG. 19D, a surface electrode 7 is formed on the front surface of the drift layer 6 through a vapor deposition process or any other suitable process. [0009] As shown in FIG. 20, the electron source 10'' illustrated in FIG. 18 is used, for example, as an electron source of a display. In a display illustrated in FIG. 20, a faceplate 50 composed of a flat-plate-shaped glass substrate is set at a position opposed to the electron source 10''. The surface of the faceplate 50 opposed to the electron source 10'' is formed with a collector electrode (hereinafter referred to as "anode electrode") 21 composed of a transparent conductive film (e.g. ITO film). The surface of the anode electrode 21 opposed to the electron source 10'' is provided with fluorescent materials formed in units of pixels, and block stripes made of black material and formed between the fluorescent materials. Each of the fluorescent materials applied onto the surface of the anode electrode 21 opposed to the electron source 10'' can give out a visible light in response to electrons emitted from the electron source 10''. The electrons emitted from the electron source 10'' are accelerated by a certain voltage applied to the anode electrode 21, and brought into collision with the fluorescent materials in the form of highly energized electrons. The fluorescent materials used herein can exhibit luminescent colors R (red), G (green) and B (blue), respectively. The faceplate 50 is spaced apart from the electron source 10'' by a rectangular frame (not shown). The space formed between the faceplate 50 and the electron source 10'' are hermetically sealed and kept in vacuum. [0010] The electron source 10'' illustrated in FIG. 20 includes an insulative substrate 11 composed of a glass substrate having an insulation performance, a plurality of lower electrodes 12 arranged in parallel with each other on one surface of the insulative substrate 11, a plurality of polycrystalline silicon layers 3 each formed to be superimposed on the corresponding lower electrode 12, and a plurality of drift layers 6 each composed of oxidized porous polycrystalline silicon layers and each formed to be superimposed on the corresponding polycrystalline silicon layer. The electron source 10'' further includes a plurality of isolating layers 16 composed of a polycrystalline silicon layer and disposed to fill in the respective spaces between the adjacent drift layers 6, between the adjacent polycrystalline silicon layers 3 and between the adjacent lower electrodes 12, and a plurality of surface electrodes 7 arranged in parallel with each other on the drift layers 6 and the isolating layers 16 to extend across the drift layers 6 and the isolating layers 16 in a direction orthogonal to the longitudinal direction of the lower electrodes 12. [0011] In the electron source 10'' illustrated in FIG. 20, the combination of the drift layers 6, the polycrystalline silicon layers 3 and the isolating layers 16 serves as an electron transit section 5. As shown in FIG. 21, the electron transit section 5 is sandwiched between the plurality of lower electrodes 12 arranged in parallel with each other on the one surface of the insulative substrate 11, and the plurality of the surface electrodes 7 arranged in parallel with each other in the plane parallel to the one surface of the insulative substrate 11 to extend in a direction orthogonal to the longitudinal direction of the lower electrodes 12. In this connection, there has also been known another electron source having an electron transit section 5 comprised only of the drift layers 6 and the isolating layers 16 without any polycrystalline silicon layer 3 interposed between the drift layer 6 and the lower electrode 12. [0012] In this electron source 10'', the drift layers 6 are partly sandwiched by the respective regions corresponding to the cross points between the plurality of lower electrodes 12 arranged in parallel with each other on the one surface of the insulative substrate 11, and the plurality of the surface electrodes 7 arranged in parallel with each other to extend in a direction orthogonal to the longitudinal direction of the lower electrodes 12. Thus, it can be designed to appropriately select a target pair of the surface electrode 7 and the lower electrode 12 and apply a certain voltage between the selected pair so as to act a strong electric field on the region corresponding to the cross point between the selected pair of the surface electrode 7 and the lower electrode 12 to allow electrons to be emitted from the region. That is, a plurality of electron source elements 10a each composed of the lower electrode 12, the polycrystalline silicon layer 3, the drift layer 6 and the surface electrode 7 are formed, respectively, at the cross points of a matrix (lattice) composed of the plurality of lower electrodes 12 and the plurality of surface electrodes 7. Thus, electrons can be emitted from any desired electron source element 10a by applying a certain voltage to the corresponding pair of the surface electrode 7 and the lower electrode 12. The electron source elements 10a are formed in one-to-one correspondence with the pixels. [0013] The drift layers 6 in the electron source 10'' illustrated in FIG. 20 are prepared according to the following process. A plurality of lower electrodes 12 are first formed on one surface of an insulative substrate 11. Subsequently, a non-doped polycrystalline silicon 3 is formed on the whole area of the one surface of the insulative substrate 11 through a plasma CVD process, a low-pressure CVD process or any other suitable process at a substrate temperature of 400.degree. C. or more (e.g. 400.degree. C. to 600.degree. C.). Then, portions of the polycrystalline silicon layer 3 superimposed on the lower electrodes 12 are anodized in an electrolyte containing a hydrofluoric solution to form a plurality of polycrystalline silicon layers. Each of the polycrystalline silicon layers includes a plurality of porous polycrystalline silicon grains and a number of nanometer-order silicon nanocrystals. Then, the porous polycrystalline silicon layers are oxidized through a rapid heating process or electrochemical oxidation process to form a plurality of drift layers 6. Each of the drift layers 6 includes a plurality of polycrystalline silicon grains each having a surface formed with a thin silicon oxide film, and a number of nanometer-order silicon nanocrystals each having a surface formed with a silicon oxide film. [0014] As described above, the production process of the electron source 10'' illustrated in FIG. 20 comprises the steps of forming the lower electrodes 12 on the front surface of the insulative substrate 11, forming the non-doped polycrystalline silicon 3 on the whole area of the front surface of the insulative substrate 11, anodizing the portions of the polycrystalline silicon layer 3 superimposed on the lower electrodes 12 to form the porous polycrystalline silicon layers, and oxidizing the porous polycrystalline silicon layers to form the drift layers 6. [0015] That is, in the production process of the electron source 10'' illustrated in FIG. 20, the drift layers 6 are formed base on the polycrystalline silicon layer 3 formed on the lower electrode 12. In this process, if some defect, such pinholes, is generated during the course of forming the polycrystalline silicon layer 3, it will be likely to cause a defect of the drift layers 6. This causes the in-plane nonuniformity of the electric field applied to the drift layer, and increased in-plane variation in electron emission characteristic. Consequently, a display is involved in problems of increased unevenness of brightness, and shortened durability due to accelerated deterioration in a portion of the drift layers 6 subject to strong field intensity. Further, due to the defect of the drift layers 6, the electron source 10'' illustrated in FIG. 20 has a problem of increased variation in electron emission characteristic between production lots. [0016] Similarly, in the electron source 10'' illustrated in FIG. 18, some defect such pinholes generated during the course of forming the polycrystalline silicon layer 3 causes a defect of the drift layer 6. This causes a problem of increased variation in electron emission characteristic between production lots, or increased in-plane variation in electron emission characteristic of an electron source having an enlarged area. Further, the electron source 10'' also has a problem of shortened durability due to accelerated deterioration in a portion of the drift layer 6 subject to strong field intensity DISCLOSURE OF INVENTION [0017] In view of the above problems, it is therefore an object of the present invention to provide an electron source having reduced in-plane variation in electron emission characteristic as compared to the conventional electron sources, and to provide a method of producing such an electron source. [0018] In order to achieve the above-mentioned object, according the present invention, there is provided an electron source (field emission-type electron source) which includes an insulative substrate, and an electron source element formed on the side of one surface (front surface) of the insulative substrate. This electron source element has a lower electrode, a surface electrode, and a drift layer (strong-field drift layer) composed of polycrystalline silicon. The drift layer is disposed between the lower and surface electrodes. The strong-field drift layer allows electrons to pass therethrough according to an electric field generated when a certain voltage is applied to the lower and surface electrodes in such a manner that the surface electrode has a higher potential than that of the lower electrode. Further, a buffer layer having an electrical resistance greater than that of the polycrystalline silicon is provided between the drift layer and the lower layer. [0019] According to this electron source, defects otherwise generated in the drift layer can be minimized to achieve the in-plane uniformity of the electric field applied to the drift layer. Thus, the in-plane variation in electron emission characteristic can be reduced as compared to the conventional electron sources. [0020] In the electron source according to the present invention, the buffer layer may include (or be composed of) an amorphous layer. This buffer layer can be readily formed at a relatively low temperature. In particular, if the amorphous layer is an amorphous silicon layer, it can be formed through a commonly used semiconductor production process. [0021] In the electron source according to the present invention, a plural number of the electron source elements may be formed on the side of the front surface of the insulative substrate. Further, the insulative substrate may include (or be composed of) a glass substrate allowing infrared rays to transmit therethrough. The buffer layer may include (or be composed of) a portion of a film which is made of a material capable of absorbing infrared rays and formed to cover the whole area on the side of the front surface of the insulative substrate before the formation of the strong-field drift layer. According to this electron source, when the insulative substrate is heated from the side of another surface (back surface) opposite to the front surface to form the drift layer, the temperature distribution on the side of the front surface can be uniformed irrespective of the pattern of the lower electrode. In addition, as comparted to an electron source in which a film serving as the buffer layer is formed only in the region where it is superimposed on the lower electrode, the in-plane variation in properties of the drift layer can be minimized to reduce the in-plane variation in electron emission characteristic. Continue reading about Field emission-type electron source and method of producing the same... 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