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Ferroelectric memory devices

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Title: Ferroelectric memory devices.
Abstract: Forming a ferroelectric memory device can include forming an insulating layer on a substrate, forming a sacrificial layer on the first insulating layer so that the insulating layer is between the sacrificial layer and the substrate, and forming a contact hole extending through the sacrificial layer and the insulating layer. A conductive contact plug can be formed in the contact hole. After forming the conductive contact plug in the contact hole, the sacrificial layer can be removed so that the conductive contact plug extends beyond the insulating layer, and so that sidewalls of the conductive contact plug extending beyond the insulating layer are exposed. A first electrode can be formed on exposed portions of the conductive contact plug, a ferroelectric layer can be formed on the first electrode, and a second electrode can be formed on the ferroelectric layer such that the ferroelectric layer is between the first and second electrodes. Related structures are also discussed. ...


- Raleigh, NC, US
Inventor: Moon-Sook Lee
USPTO Applicaton #: #20060183252 - Class: 438003000 (USPTO) - 08/17/06 - Class 438 


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Related Patent Categories: Semiconductor Device Manufacturing: Process, Having Magnetic Or Ferroelectric Component
The Patent Description & Claims data below is from USPTO Patent Application 20060183252, Ferroelectric memory devices.





RELATED APPLICATION

[0001] This application claims the benefit of priority as a divisional application from U.S. patent application Ser. No. 10/273,115 filed Oct. 17, 2002, which claims priority from Korean Patent Application No. 2001-64252, filed on Oct. 18, 2001. The disclosures of the above referenced U.S. and Korean patent applications are incorporated herein in their entirety by reference.

FIELD OF THE INVENTION

[0002] The present invention relates to ferroelectric random access memory (FRAM) devices and related methods of fabrication.

BACKGROUND OF THE INVENTION

[0003] A ferroelectric material exhibits polarization when an external electric field is applied, and maintains the polarization even after removing the external electric field. Also, ferroelectric materials may control a direction of spontaneous polarization with a change of the electric field. Ferroelectric materials include PZT[Pb(Zr, Ti)O.sub.3], SBT[SrBi.sub.2Ta.sub.2O.sub.9], and the like. These characteristics of ferroelectric materials may be used to provide binary memory devices. Extensive studies for applications of ferroelectric random access memory (FRAM) devices have thus been initiated.

[0004] Generally, an FRAM device has a planar capacitor structure comprising planar upper and lower electrodes, and a ferroelectric thin layer between the electrodes. The upper and lower electrodes may be made of noble metals such as iridium or platinum or oxides thereof. The ferroelectric thin layer can be formed by a sol-gel method, sputtering, or chemical vapor deposition (CVD). However, as an integration level of a semiconductor memory device increases, a cell area of individual FRAM devices may decrease. Hence, the capacitor area included in the cell may also be reduced. Therefore, to provide a sufficient capacitance, a three-dimensional capacitor structure may be provided so that the surface area of the capacitor may be increased. To form such a three-dimensional capacitor structure, however, steps may need to be added to conventional fabricating methods. Since the additional steps may add significant cost in fabricating the semiconductor device, the number of additional steps is preferably reduced.

[0005] In a dynamic random access memory device (DRAM) having a similar structure to an FRAM device, a capacitor over bit line (COB) capacitor including both a storage node contact and a capacitor lower electrode may be employed. Unlike a DRAM, however, a capacitor lower electrode of an FRAM capacitor may be formed of a noble metal, but the storage node contact may preferably be formed of another material. This is because an amount of the noble metal is preferably reduced to reduce the fabrication costs of the semiconductor device. In addition, some FRAM electrode materials may not be desirable as storage node contacts due to a relatively high electrical resistance and/or relatively poor gap fill characteristics.

[0006] In other approaches, a cylinder-type COB capacitor may be used to increase the area of the lower electrode. In this case, however, a node separation process of the lower electrode may be difficult to provide using chemical mechanical polishing (CMP). In addition, the cylinder may be hardly formed when the lower electrode material suffers from degradation of a step coverage characteristic. Accordingly, the cylinder-type COB capacitor structure may not be suitable for FRAM devices.

[0007] In addition, a stacked capacitor structure may not be suitable for FRAM devices. Forming a stacked capacitor structure may include stacking a relatively thick lower electrode on the contact plug, then patterning the resulting structure where the lower electrode is stacked. Because most of a high-priced material making up the lower electrode layer may be removed, fabrication costs may be unnecessarily increased. Also, an etch process for forming the lower electrode may be difficult to perform.

[0008] FIG. 1 illustrates a three-dimensional FRAM capacitor that may reduce problems discussed above.

[0009] Referring to FIG. 1, a contact plug is formed as known to those skilled in the art. A lower interlayer insulating layer 12 is formed on a substrate 100. A lower contact plug 14 is formed to penetrate the lower interlayer insulating layer 12. An upper contact plug 18 is formed to be in contact with the lower contact plug 14. Forming the upper contact plug 18 comprises forming an upper interlayer insulating layer (not shown) on an entire surface of the semiconductor substrate including the lower contact plug 14 and insulating layer 12. The upper interlayer insulating layer is then patterned to form an upper contact hole exposing the lower contact plug 14. The upper contact plug 18 is formed to fill the upper contact hole. Thereafter, the upper interlayer insulating layer is removed to expose both the upper contact plug 18 and the lower interlayer insulating layer 12.

[0010] A lower electrode 220, a ferroelectric layer pattern 240, and an upper electrode 260 are sequentially formed to cover the exposed upper contact plug 18 to provide a capacitor 200. In these steps, the upper contact plug 18 is exposed on the lower interlayer insulating layer 12, thereby forming the three-dimensional lower electrode 220. As a result, a capacitance of the capacitor may be increased. Examples of the foregoing conventional method are disclosed, for example, in U.S. Pat. No. 5,581,436, U.S. Pat. No. 5,499,207, and U.S. Pat. No. 6,043,526.

[0011] Additional steps, however, may need to be taken to provide the three dimensional structure of the upper contact plug. That is, additional steps of stacking, patterning, and removing the upper interlayer insulating layer may be required. In addition, as the integration level of the semiconductor device increases, a margin of an exposure process when patterning the upper interlayer insulating layer may be reduced. Therefore, a likelihood of misalignment may be increased while patterning the upper interlayer insulating layer, and misalignment may cause a decrease in a contact area between the upper and lower contact plugs.

SUMMARY OF THE INVENTION

[0012] According to embodiments of the present invention, methods of forming a ferroelectric memory device can include forming an insulating layer on a substrate, and forming a sacrificial layer on the first insulating layer so that the insulating layer is between the sacrificial layer and the substrate. A contact hole can be formed extending through the sacrificial layer and the insulating layer, and a conductive contact plug can be formed in the contact hole. After forming the conductive contact plug in the contact hole, the sacrificial layer can be removed so that the conductive contact plug extends beyond the insulating layer, and so that sidewalls of the conductive contact plug extending beyond the insulating layer are exposed. A first electrode can be formed on exposed portions of the conductive contact plug, a ferroelectric layer can be formed on the first electrode, and a second electrode can be formed on the ferroelectric layer such that the ferroelectric layer is between the first and second electrodes.

[0013] According to additional embodiments of the present invention, methods of forming a ferroelectric memory devices can include forming an insulating layer on a substrate, and forming a contact hole extending through the insulating layer. A conductive contact plug can be formed in the contact hole wherein the conductive contact plug extends beyond the insulating layer so that sidewalls of the conductive contact plug extending beyond the insulating layer are exposed. Moreover, a width of portions of the conductive contact plug extending beyond the insulating layer can be greater than a width of portions of the conductive contact plug extending through the insulating layer. In addition, a first electrode can be formed on exposed portions of the conductive contact plug, a ferroelectric layer can be formed on the first electrode, and a second electrode can be formed on the ferroelectric layer such that the ferroelectric layer is between the first and second electrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1 is a cross-sectional view illustrating a conventional ferroelectric capacitor;

[0015] FIGS. 2 through 6 are cross-sectional views illustrating structures and methods of fabricating ferroelectric capacitors according to embodiments of the present invention.

[0016] FIG. 7 is a cross-sectional view illustrating structures and methods of fabricating ferroelectric capacitors according to additional embodiments of the present invention.

DETAILED DESCRIPTION

[0017] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which typical embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the relative sizes of regions may be exaggerated for clarity. It will be understood that when an element is referred to as being "on" to another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. Terms used herein are to be given their ordinary meaning unless explicitly defined otherwise herein.

[0018] FIGS. 2 through 6 are cross-sectional views illustrating methods of fabricating ferroelectric capacitors and related structures and devices according to embodiments of the present invention.

[0019] Referring to FIG. 2, a device isolation layer 11 is formed to define an active region on a semiconductor substrate 10. After forming a gate insulating layer on the active region, a gate layer and a capping layer are sequentially formed on an entire surface of the substrate where the gate insulating layer is formed. The capping layer and the gate layer are successively patterned to form gate electrodes 13 on respective gate insulating layers.

[0020] Using the gate electrode as an ion implantation mask, impurity ions can be implanted into portions of the active region of the substrate 10 to form source/drain regions 15 in the active region adjacent to the gate electrodes 13. Pads 17 are formed in contact with respective source/drain regions 15 as known to those skilled in the art. A first interlayer insulating layer 21 (also referred to as an insulating layer) is formed on an entire surface of a semiconductor substrate including the pads 17. The first interlayer insulating layer 21 can be subsequently patterned to provide bit line contact holes exposing predetermined ones of the pads 17 in contact with respective source/drain regions 15. A conductive layer can be provided filling the bit line contact hole, and patterned to provide a bit line contact plug and a bit line. A bit line contact plug can fill a bit line contact hole and provide a bit line crossing thereon. A bit line contact plug can thus be electrically coupled to a drain 15 through a respective pad 17.

[0021] Second and third interlayer insulating layers 31 and 35 are sequentially formed on the bit line and the first interlayer insulating layer 21. The second and third interlayer insulating layers 31 and 35 are made of materials having etch selectivities with respect to each other. In addition, first and second etch stop layers 33 and 37 may be additionally formed on the second and third interlayer insulating layers 31 and 35. The first, second, and third interlayer insulating layers 21, 31, and 35 can be made of silicon oxide. At this time, the third interlayer insulating layer 35 can be made of a material whose etch rate is higher than that of the second interlayer insulating layer 31 with respect to an etch process using a silicon oxide layer etch recipe. For example, the second interlayer insulating layer 31 may be made of high density plasma (HDP) oxide or tetra ethyl ortho silicate (TEOS). The third interlayer insulating layer 35 may be made of spin on glass (SOG) or boro-phospho-silicate-glass (BPSG). Accordingly an isotropic etch can be provided such that the third interlayer insulating layer 35 can be etched at a higher rate than the second interlayer insulating layer 31.

[0022] Referring to FIG. 3, the second etch stop layer 37, the third interlayer insulating layer 35, the first etch stop layer 33, the second interlayer insulating layer 31, and the first interlayer insulating layer 21 are successively patterned to form contact holes 39 of the capacitor lower electrodes. Moreover, the layers 21, 31, 33, 35, and 37 can be patterned using a single etch mask. The contact holes 39 expose respective pads 17 of the source/drain regions 15.

[0023] The patterning for forming the contact holes 39 may employ an anisotropic etch process, an isotropic etch process, or both. In particular, the contact holes 39 can be formed using an anisotropic etch, and a width of the contact holes 39 can be increased using an isotropic etch. In the isotropic etch used to increase the width of the contact hole 39, an etch rate of the third interlayer insulating layer 35 can be higher than that of the second interlayer insulating layer 31, so that a width A of the contact hole 39 through the third interlayer insulating layer 35 is greater than a width B of the contact hole 39 through the second interlayer insulating layer 31.

[0024] The patterning for forming the contact hole 39 may employ a photoresist pattern such as an etch mask. Alternatively, the second etch stop layer 37 can be patterned using the photoresist pattern as an etch mask to form a second etch stop layer pattern 37'. Thereafter, the second etch stop layer pattern 37' may be used as a hard mask for forming the contact hole 39. In case the second etch stop layer pattern 37' is used as the hard mask, the second etch stop layer pattern 37' is formed to have an opening whose width is smaller than that of the contact hole in the second interlayer insulating layer 31. The width of the opening is preferably adjusted in consideration of a thickness of the second interlayer insulating layer 31 that is recessed during the isotropic etch process.

[0025] Referring to FIG. 4, the photoresist pattern and the second etch stop layer pattern 37' can be removed to expose a top surface of the third interlayer insulating layer 35. A conductive layer (not shown) is then stacked to form a contact plug layer on an entire surface of the semiconductor substrate including the third interlayer insulating layer 35 where the second etch stop layer pattern 37' has been removed and in the contact holes 39. Thereafter, the conductive layer can be planarized until the top surface of the third interlayer insulating layer is exposed, thereby forming contact plugs 41 filling the contact holes 39. In the alternative, the etch stop layer pattern 37' may be removed after forming the contact plugs 41. For example, the second etch stop layer pattern 37' may be removed during the planarizing etch process.

[0026] The conductive layer for forming the contact plugs 41 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering. The conductive layer can be made of one selected from the group consisting of tungsten, polysilicon, titanium nitride, titanium, titanium silicide, and cobalt silicide. According to first embodiments of the present invention, a titanium nitride layer and a titanium layer can be sequentially deposited using CVD or ALD, and then remaining portions of the contact holes can be filled with a tungsten layer. In this case, the titanium nitride layer and the titanium layer may serve as barrier metals.

[0027] Referring FIG. 5, the exposed third interlayer insulating layer 35 can be removed to expose the first etch stop layer 33. The third interlayer insulating layer 35 can be removed using an etch recipe that has the etch selectivity with respect to both the contact plugs 41 and the first etch stop layer 33 so that the contact plugs 41 and the first etch stop layer are not significantly affected when removing the interlayer insulating layer 35. As a result, upper portions (hereinafter referred to as "projections 411") of contact plugs 41 project over the first etch stop layer 33, whereas lower portions of the contact plugs 41 fill the contact holes 39 in the first and second interlayer insulating layers 21 and 31.

[0028] Accordingly, the third interlayer insulating layer 35 may serve as a sacrificial layer that is removed during processing and is not present in the completed ferroelectric memory device. While silicon oxides are discussed above, other materials may be used to provide the sacrificial layer. Moreover, it is not required that the sacrificial layer be insulating because it is not maintained in the completed ferroelectric memory device.

[0029] The first etch stop layer 33 can be made of a material providing reliable adhesion to both the second interlayer insulating layer 31 and the contact plug 41, and also providing etch selectivity with respect to the third interlayer insulating layer 35. In other words, the first etch stop layer may be resistant to an etch used to remove the third interlayer insulating layer 35. The first etch stop layer 33 can be made of a material selected from the group consisting of a silicon nitride layer, a silicon nitride oxide layer, a titanium oxide layer, a titanium nitride layer, a double layer of a titanium nitride layer/a titanium layer, and a titanium aluminum nitride layer. Reliable adhesion between the first etch stop layer 33 and the contact plugs 41 can reduce etching of the second interlayer insulating layer 31 during an etch used to remove the third interlayer insulating layer 35. In addition, the first etch stop layer 33 preferably provides reliable adhesion with respect to a lower capacitor electrode that will be formed during a subsequent process. The removed second etch stop layer 37 can be made of the same material as the first etch stop layer 33.

[0030] Referring to FIG. 6, a lower electrode layer, a ferroelectric layer, and an upper electrode layer can be sequentially formed on an entire surface of the semiconductor substrate including the contact plugs 41 where the third interlayer insulating layer 35 is removed. Thereafter, the lower electrode layer, the ferroelectric layer, and the upper electrode layer can be successively patterned to form ferroelectric capacitors 20. Each ferroelectric capacitor 20 can include lower electrode 22, a ferroelectric layer 24, and an upper electrode 26 that sequentially cover the projections 411.

[0031] The lower and upper electrode layers may each comprise a noble metal such as one selected from platinum, iridium, ruthenium, osmium, palladium, and rhodium, and their conductive oxides. The ferroelectric layer may comprise a ferroelectric material such as one selected from PZT[Pb(Zr, Ti)O.sub.3], SrTiO.sub.3, BaTiO.sub.3, BST[(Ba, Sr)TiO.sub.3], SBT(SrBi.sub.2Ta.sub.2O.sub.9), (Pb, La)(Zr, Ti)O.sub.3, and Bi.sub.4Ti.sub.3O.sub.12. The ferroelectric material may be stacked by either sputtering or a sol-gel method and annealed in an oxidizing ambient of about 700.degree. C. to form the ferroelectric layer. Alternately, for forming the ferroelectric layer, the ferroelectric material may be stacked by CVD and annealed at 400 to 500.degree. C. Other techniques for forming ferroelectric materials may also be used.

[0032] In addition, an adhesion layer (not shown) and/or an oxygen barrier layer (not shown) may be additionally stacked before forming the lower electrode layer. An adhesion layer can be selected from the group consisting of a titanium layer, a double layer of a titanium nitride layer/a titanium layer, and a titanium aluminum nitride layer. An oxygen barrier layer can be made of iridium. The oxygen barrier layer can be formed when the lower electrode layer is made of platinum or the like that is not suitable for an oxygen barrier material.

[0033] FIG. 7 is a cross-sectional view illustrating methods of fabricating a ferroelectric capacitor in accordance with additional embodiments of the present invention. Steps illustrated in FIGS. 2 through 5 may be the same as those of embodiments illustrated in FIG. 7. Description of those steps discussed with respect to FIGS. 2-5 will be omitted here.

[0034] Referring to FIGS. 5 and 7, a lower electrode layer is formed on an entire surface of a semiconductor substrate including etch stop layer 33 where the third interlayer insulating layer 35 is removed. The lower electrode layer is patterned to form lower electrodes 22. A ferroelectric layer and an upper electrode layer are sequentially stacked on an entire surface of the semiconductor substrate including the lower electrodes 22. The upper electrode layer and the ferroelectric layer can be successively patterned to form a ferroelectric layer pattern 24' and an upper electrode 26' that cover the lower electrodes 22. In the present embodiment, a single ferroelectric layer pattern 24' and a single upper electrode 26' that are sequentially stacked can cover at least two lower electrodes 22. In other words, the ferroelectric layer 24' and the upper electrode 26' can be formed after patterning the lower electrodes 22, and the ferroelectric layer 24' and the upper electrode 26' can extend onto separate lower electrodes 22.

[0035] An adhesion layer and an oxygen barrier layer may be additionally formed between the projections 411 and the lower electrodes 22. Methods and materials of fabricating the ferroelectric layer, and the upper and lower electrode layers may be the same as methods and materials discussed above with respect to FIG. 6. In addition, adhesion layers and oxygen barrier layers may be formed as discussed above with respect to FIG. 6.

[0036] According to the present invention, three-dimensional capacitors can be fabricated with a reduced number of fabrication steps. As a result, a ferroelectric memory device with a sufficient capacitance can be economically fabricated. In addition, misalignment can be reduced, thereby providing semiconductor devices with increased reliability.

[0037] According to additional embodiments of the present invention, methods of fabricating ferroelectric memory devices can include forming a contact plug penetrating an interlayer insulating layer, recessing the interlayer insulating layer, and projecting an upper portion of the contact plug. The ferroelectric memory device can include a substrate where a conductive region is formed, and an interlayer insulating layer stacked on the substrate. The interlayer insulating layer can include a contact hole exposing the conductive region. The contact hole can be filled with a contact plug having a projection over the interlayer insulating layer. The projection of the contact plug can be covered with a capacitor including a lower electrode, a ferroelectric layer pattern, and an upper electrode. A width of the projection can be greater than that of the contact hole.

[0038] A width of the lower electrode can be greater than that of the projection of the contact plug. An etch stop layer can be additionally disposed on the interlayer insulating layer. In this case, the etch stop layer can be one selected from the group consisting of a silicon nitride layer, a silicon nitride oxide layer, a titanium oxide layer, a titanium nitride layer, a double layer of a titanium nitride layer/a titanium layer, and a titanium aluminum nitride layer.

[0039] Methods of fabricating a ferroelectric memory device can also include sequentially stacking lower and upper interlayer insulating layers on a substrate where a conductive region is formed. The upper and lower interlayer insulating layers can be successively patterned to form a contact hole exposing the conductive region. A conductive contact plug can be formed to fill the contact hole. The upper interlayer insulating layer can then be removed to expose the lower interlayer insulating layer such that an upper portion of the contact plug is projected. At this time, the projected upper portion of the contact plug projects beyond the lower interlayer insulating layer. Thereafter, a lower electrode, a ferroelectric layer pattern, and an upper electrode can be formed sequentially to cover the projected upper portion of the contact plug and to form a capacitor. The contact hole can be formed such that a width of the contact hole formed in the upper interlayer insulating layer is greater than that of the contact hole formed in the lower interlayer insulating layer.

[0040] In addition, the upper interlayer insulating layer can be made of a material having an etch selectivity with respect to the lower interlayer insulating layer. Forming the contact hole may comprise successively etching the upper and lower interlayer insulating layers using an anisotropic etch to form the contact hole exposing the conductive region. A width of the contact hole can then be increased. When increasing the width of the contact hole, a sidewall of the contact hole can be etched using an isotropic etch process. The isotropic etch process can employ an etch recipe in which an etch rate of the upper interlayer insulating layer is higher than that of the lower interlayer insulating layer.

[0041] In addition, an etch stop layer can be additionally formed on the lower interlayer insulating layer before forming the upper interlayer insulating layer. The etch stop layer can increase a margin of an etch process and provide a reliable adhesion between the lower interlayer insulating layer and the lower electrode. In addition, another etch stop layer may be provided on the upper interlayer insulating layer.

[0042] Forming the capacitor can include sequentially stacking a lower electrode layer, a ferroelectric layer, and an upper electrode layer on an entire surface of the resulting structure including the upper portion of the contact plug projecting beyond the lower interlayer insulating layer. Then, the lower electrode layer, the ferroelectric layer, and the upper electrode layer can be successively patterned.

[0043] Forming the capacitor may include forming the lower electrode layer on an entire surface of the resultant structure including the upper portion of the contact plug projecting beyond the lower interlayer insulating layer. The lower electrode layer may be patterned to form the lower electrode covering the projected upper portion of the contact plug. The ferroelectric layer and the upper electrode layer can be sequentially stacked on an entire surface of the semiconductor substrate where the lower electrode is formed. Thereafter, the upper electrode layer and the ferroelectric layer can be successively patterned to form an upper electrode and a ferroelectric layer pattern.

[0044] When patterning the upper electrode layer and the ferroelectric layer, a single ferroelectric layer pattern and a single upper electrode that are sequentially stacked may cover at least two lower electrodes.

[0045] It should be noted that many variations and modifications might be made to the embodiments described above without substantially departing from the principles of the present invention. All such variations and modifications are intended to be included herein within the scope of the present invention, as set forth in the following claims.

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stats Patent Info
Application #
US 20060183252 A1
Publish Date
08/17/2006
Document #
File Date
04/18/2014
USPTO Class
Other USPTO Classes
International Class
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