| Fabrication of stacked die and structures formed thereby -> Monitor Keywords |
|
|
 
Fabrication of stacked die and structures formed therebyRelated Patent Categories: Semiconductor Device Manufacturing: Process, Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor, Assembly Of Plural Semiconductive Substrates Each Possessing Electrical Device, Stacked Array (e.g., Rectifier, Etc.)Fabrication of stacked die and structures formed thereby description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060128061, Fabrication of stacked die and structures formed thereby. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This U.S. Patent application is a divisional of U.S. patent application Ser. No. 10/958,511 filed Oct. 4, 2004. FIELD OF THE INVENTION [0002] The present invention generally relates to the field of microelectronic devices, and more particularly to methods of fabricating stacked die structures without the use of an interfacial glue. BACK GROUND OF THE INVENTION [0003] Integrated circuits form the basis for many electronic systems. An integrated circuit may include a vast number of transistors and other circuit elements that may be formed on a single semiconductor wafer or chip and may be interconnected to implement a desired function. [0004] Many modern electronic systems are created through the use of a variety of different integrated circuits; each integrated circuit performing one or more specific function. For example, computer systems may include at least one microprocessor and a number of memory chips. Conventionally, each of these integrated circuits are formed on a separate chip, packaged independently and interconnected on, for example, a printed circuit board (PCB). [0005] As integrated circuit technology progresses, there is a growing desire for a "system on a chip", in which the functionality of all of the integrated circuit devices of the system are packaged together without a conventional PCB. In practice, various "system modules" have been introduced that electrically connect and package integrated circuit devices which are fabricated on the same or on different semiconductor wafers. Initially, system modules have been created by simply stacking two chips, e.g., a logic and memory chip, one on top of the other in an arrangement commonly referred to as chip-on-chip structure. Subsequently, multi-chip module (MCM) technology has been utilized to stack a number of chips on a common substrate to reduce the overall size and weight of the package, which directly translates into reduced system size. BRIEF DESCRIPTION OF THE DRAWINGS [0006] While the specification concludes with claims particularly pointing out and distinctly claiming certain embodiments of the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which: [0007] FIGS. 1a-1e represent structures according to an embodiment of the present invention. [0008] FIG. 2 represents a structure according to an embodiment of the present invention. [0009] FIG. 3 represents a structure according to another embodiment of the present invention. [0010] FIG. 4 represents a system according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PRESENT INVENTION [0011] In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views. [0012] Methods and associated structures of forming and utilizing a microelectronic device are described. Those methods comprise forming a bond between a non-device side of a first die and a non-device side of a second die, without the use of an interfacial glue. In this manner, improved thermal and electrical contact, as well as a decrease in stress between the bonded die, can be achieved. [0013] FIGS. 1a-1e illustrate an embodiment of a method of forming stacked die structures. FIG. 1a illustrates a device wafer 100. The device wafer 100 may be comprised of materials such as, but not limited to, silicon, silicon-on-insulator, silicon on diamond, or combinations thereof. The device wafer 100 may comprise a device portion 103, and a non-device portion 104. The non-device portion 104 of the device wafer 100 may comprise a first thickness 106. The device wafer 100 may comprise a plurality of die 101, as are known in the art. The plurality of die 101 may comprise various functionalities, such as, but not limited to, a memory functionality and/or a logic functionality, as are well known in the art. [0014] The non-device portion 104 of the device wafer 100 may be thinned utilizing a grinding and/or a polishing technique, as are known in the art (FIG. 1b). The non-device portion 104 of the device wafer 100 may be thinned to a thinned thickness 108. In one embodiment, the thinned thickness 108 may range from about 50 to about 200 microns. The device wafer 100 may then be separated into a plurality of individual die 102 utilizing methods well known to those skilled in the art, such as but not limited to wafer sawing, which serve to separate the plurality of die 101 from each other (FIG. 1c). [0015] The plurality of individual die 102 may comprise a device side 110 and a non-device side 112. In one embodiment, the non-device side 112 may comprise silicon. The device side 110 may comprise various circuit elements, such as but not limited to transistors, resistors etc. as are well known in the art. In one embodiment, a first individual die 102a may comprise a device side 110a and a non-device side 112a (FIG. 1d). A second individual die 102b may comprise a device side 110b and a non-device side 112b. The non-device side 112a of the first individual die 102a may be brought into contact with the non-device side 112b of the second individual die 102b to form a stacked die structure 116 (FIG. 1e). [0016] Upon contacting the non-device side 112a of the first individual die 102a with the non-device side 112b of the second individual die 102b, a bond 114 may be formed by direct silicon to silicon bonding between the non-device side 112a of the first individual die 102a and the non-device side 112b of the second individual die 102b. The bond 114 may be formed due to Van der Waal forces that may develop between the non-device side 112a (which may comprises silicon) of the first individual die 120a and the non-device side 112b (which also preferably comprises silicon) of the second individual die 102b. In one embodiment, the bond 114 can be further strengthened by heating the stacked die structure 116 to a temperature up to about 450 degrees Celsius, and in another embodiment, by heating from about 250 degrees to about 450 degrees Celsius. [0017] Forming the bond 114 by utilizing direct silicon to silicon bonding according to the methods of the present embodiment alleviates the need for using an interfacial glue, i.e., polymers, adhesives, solders, and other such materials commonly used to join one die to another, as are well known in the art. The elimination of such an interfacial glue, or joining material, to form the bond 114 between the first individual die 102a and the second individual die 102b results in better thermal and electrical contact between the die, due to the low coefficient of thermal expansion (CTE) differences between the die. The CTE differences between the die may be approximately zero when both of the die comprise silicon, for example. [0018] Thus, deleterious thermal barriers may be eliminated between the die joined according to the methods of the present embodiment. In addition, stress between die joined according to the present embodiment are greatly reduced, if not eliminated due to the matching of the CTE's between the joined die. Yet another advantage of joining the die without the use of interfacial glue is that the directly bonded die reinforce each other by increasing rigidity and reducing the strain that would typically be introduced by joining the die with an interfacial glue. Increasing rigidity and reducing strain decreases undesirable shifts in electrical parameters. Yet another advantage of the present embodiment is that the mechanical strength of the bond 114 is improved by utilizing direct silicon to silicon bonding, and in one embodiment the mechanical strength of the bond may comprise at least about 1500 KPa. [0019] FIG. 2 depicts an embodiment of a stacked die structure 216 that may comprise a first individual die 202a, a second individual die 202b, a third individual die 202c, and a fourth individual die 202d. In one embodiment, the individual die 202a, 202b, 202c, 202d may comprise various functionalities, such as but not limited to memory functionalities and/or logic functionalities. The individual die 202a, 202b, 202c, 202d may comprise device sides 210a, 210b, 210c, 210d and non-device sides 212a, 212b, 212c, 212d, respectively. In one embodiment, the non-device sides 212a, 212b, 212c, 212d may preferably comprise silicon. [0020] The non-device side 212a of the first individual die 202a may be bonded to the non-device side 212b of the second individual die 202b (by direct silicon to silicon bonding, as described above) to form a bond 214a, similar to the bond 114 in FIG. 1e. The bond 214a does not comprise an interfacial glue. In like manner, the non-device side 212c of the third individual die 202c may be bonded to the non-device side 212d of the fourth individual die 202d to form a bond 214b, that is similar to the bond 114 of FIG. 1e, and which does not comprise an interfacial glue. Continue reading about Fabrication of stacked die and structures formed thereby... Full patent description for Fabrication of stacked die and structures formed thereby Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Fabrication of stacked die and structures formed thereby patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Fabrication of stacked die and structures formed thereby or other areas of interest. ### Previous Patent Application: Compact system module with built-in thermoelectric cooling Next Patent Application: Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Fabrication of stacked die and structures formed thereby patent info. IP-related news and info Results in 0.21753 seconds Other interesting Feshpatents.com categories: Software: Finance , AI , Databases , Development , Document , Navigation , Error 174 |
 * Protect your Inventions * US Patent Office filing 
PATENT INFO |
|
