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Fabrication of lean-free stacked capacitorsRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Device Array And Selectively Interconnecting, With Electrical Circuit LayoutFabrication of lean-free stacked capacitors description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060211178, Fabrication of lean-free stacked capacitors. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION(S) [0001] The present application is a divisional of an earlier filed copending patent application with Ser. No. 10/853,628 filed on May 25, 2004, for which priority is claimed. This earlier filed copending patent application with Ser. No. 10/853,628 is in its entirety incorporated herewith by reference. [0002] The present application claims priority under 35 U.S.C. .sctn. 119 to Korean Patent Application No. P2004-8770, filed on Feb. 10, 2004, which is incorporated herein by reference in its entirety. A certified copy of Korean Patent Application No. P2004-8770 is contained in the parent copending patent application with Ser. No. 10/853,628. TECHNICAL FIELD [0003] The present invention relates generally to integrated circuit fabrication, and more particularly, to fabrication of lean-free stacked capacitors that may be used for DRAM (dynamic random access memory). BACKGROUND OF THE INVENTION [0004] FIG. 1 shows a simplified schematic of a DRAM (dynamic random access memory) cell 100 including a switching transistor 102 and a storage capacitor 104. A DRAM includes an array of such DRAM cells. When the switching transistor 102 is an NMOSFET (N-channel metal oxide semiconductor field effect transistor), the gate of the NMOSFET 102 is coupled to a word-line 106 of the DRAM, and the drain of the NMOSFET 102 is coupled to a bit-line 108 of the DRAM. [0005] In a typical DRAM array, the DRAM cells along a same column are coupled to a same bit-line, and the DRAM cells along a same row are coupled to a same word-line. The source of the NMOSFET 102 is coupled to a storage node of the storage capacitor 104. The other node of the storage capacitor 104 is coupled to a ground node. The bit-line 108 is coupled to a sense amplifier 110. [0006] The voltage across the storage capacitor 104 determines the logical level "1" or "0" stored within the DRAM cell 100. The sense amplifier 110 outputs such a stored logical level at the storage node of the storage capacitor 104. A parasitic capacitance 112, at the bit-line 108, disadvantageously deteriorates the voltage signal, Vsignal, to the sense amplifier 110 since Vsignal is directly proportional to Cs/Cp, with Cs being the capacitance of the storage capacitor 104 and Cp being the capacitance of the parasitic capacitor 112. [0007] The capacitance, Cs, of the storage capacitor 104 is desired to be maximized to provide sufficient voltage signal, Vsignal, to the sense amplifier 110 and for enhancing retention time for the DRAM cell 100. On the other-hand, the area occupied by the DRAM cell 100 is also desired to be minimized. Thus, a stacked capacitor having electrodes formed vertically upwards is used for the storage capacitor 104 of the DRAM cell 100. [0008] Capacitance of a capacitor formed with two electrodes is generally expressed as follows: C=A.epsilon./d C is the capacitance of the capacitor, and A is an area of overlap between the two electrodes. In addition, .epsilon. is the dielectric constant of the dielectric between the two electrodes, and d is the thickness of such a dielectric. [0009] FIG. 2 illustrates a cross-sectional view of a first stacked capacitor 112 and a second stacked capacitor 114. The first stacked capacitor 112 includes a first electrode 116 coupled, via a conductive plug structure 118, to a junction of a switching transistor (not shown for clarity of illustrate in FIG. 2) for a first DRAM cell formed with a semiconductor substrate 120. Similarly, the second stacked capacitor 114 includes a first electrode 122 coupled, via a conductive plug structure 124, to a junction of a switching transistor (not shown for clarity of illustrate in FIG. 2) for a second DRAM cell formed with the semiconductor substrate 120. [0010] A layer of support dielectric 126 surrounds the first electrodes 116 and 122 toward the bottom of such electrodes 116 and 122. A capacitor dielectric 128 is formed on exposed surfaces after formation of the first electrodes 116 and 122 and the support dielectric 126. A second electrode 130 is formed onto the capacitor dielectric 128, and the second electrode 130 is typically coupled to the ground node of the storage capacitor 104 as illustrated in FIG. 1. ILD (inter-level dielectric) layers 132 and 134 are formed to electrically isolate the conductive structures in FIG. 2. [0011] For maximizing capacitance of the stacked capacitors 112 and 114, the area of overlap between the first and second electrodes is desired to be maximized. Thus, the height of the first and second electrodes is desired to be maximized. However, with ever-increasing height, the adjacent first electrodes 116 and 122 that are exposed during fabrication may lean towards each-other with the support dielectric 126 being disposed just toward the bottom of the electrodes 116 and 122. [0012] In addition, the area occupied by the DRAM is desired to be further minimized with advancement of IC (integrated circuit) fabrication technology. Thus, the first electrodes 116 and 122 are desired to be disposed closer together. Such exposed and leaning electrodes 116 and 122 when disposed close enough together may disadvantageously contact each-other during fabrication resulting in malfunction of the DRAM. [0013] Referring to FIG. 3, U.S. Patent Application Publication No. US 2003/0085420 to Ito et al. discloses stacked capacitors 142 and 144 with support beams 146 disposed above the layer of support dielectric 126 for preventing leaning of the first electrodes 116 and 122. FIG. 4 shows a cross-sectional view across line A-A of FIG. 3 through the support beams 146. Elements having the same reference number in FIGS. 2, 3, 4, 5, 6, and 7 refer to elements having similar structure and function. [0014] Referring to FIGS. 3 and 4, support beams 146 are formed on the four sides of a first electrode 116. In addition, each support beam 146 is disposed between two adjacent first electrodes 116 and 122, well above the bottom support dielectric 126. Thus, the support beams 146 prevent the exposed top portions of two adjacent first electrodes 116 and 122 from leaning against each other during fabrication of the stacked capacitors 142 and 144. [0015] FIGS. 5, 6, and 7 illustrate cross-sectional views across line A-A of FIG. 3 during fabrication of the support beams 146. Referring to FIG. 5, a material comprising the support beams 146 is first patterned on a sacrificial dielectric material 148. Referring to FIGS. 5 and 6, openings 150, 152, 154, and 156 are each formed around an intersection point of the support beams 146. Referring to FIG. 7, a respective first electrode is formed at the walls of each of the openings 150, 152, 154, and 156. FIG. 7 shows the example first electrodes 116 and 122. Thereafter, the sacrificial dielectric material 148 is etched away, and the gate electric 128 and the second electrode 130 are formed onto exposed surfaces of the first electrodes and the support beams 146. [0016] With such a prior art process, the support beams 146 are formed before the stacked capacitors are formed within the openings 150, 152, 154, and 156. With such early formation of the support beams 146, subsequent etching steps may decrease the width (w) and the thickness of the support beams 146. Thus, the width and the thickness of the support beams 146 are more difficult to control in the prior art. SUMMARY OF THE INVENTION [0017] Accordingly, in a general aspect of the present invention, support structures for preventing leaning of adjacent first electrodes of stacked capacitors are formed after formation of the first electrodes. [0018] In an embodiment of the present invention, openings are formed through layers of materials including a layer of support material displaced from a bottom of the openings. A respective first electrode is formed for a respective capacitor within each of the openings. The layer of support material is patterned to form support structures around the first electrodes, after formation of the first electrodes within the openings. [0019] In an example embodiment for forming the support structures, at least one of the layers of materials toward the top of the first electrodes is etched away such that a top portion of the first electrodes is exposed and such that the support material is exposed. Masking spacers are formed with a masking material around the exposed top portions of the first electrodes. A mask structure of the masking material remains on joining portions of the support material. Exposed portions of the support material are etched away such that the support structures including the joining portions are formed from the remaining support material. Each joining portion is disposed between the first electrodes of adjacent capacitors. [0020] Further for such an example embodiment, the masking material is deposited with a thickness that is greater than 1/2 of a length of the joining portions, before forming the masking spacers. Additionally for such an example embodiment, the support structures include a respective disc that may be a circular disc surrounding each first electrode. Also for such an example embodiment, the respective disc surrounding each first electrode is further etched such that a respective beam remains for each of the joining portions as the support structures. Continue reading about Fabrication of lean-free stacked capacitors... Full patent description for Fabrication of lean-free stacked capacitors Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Fabrication of lean-free stacked capacitors patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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