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Fabrication method of semiconductor integrated circuit device

Fabrication method of semiconductor integrated circuit device description/claims

This application is a continuation of U.S. application Ser. No. 11/936,358, filed Nov. 7, 2007, which, in turn, is a continuation of U.S. application Ser. No. 11/012,225, filed Dec. 16, 2004 (now U.S. Pat. No. 7,306,957), and which application claims priority from Japanese patent application No. 2003-425616, filed on Dec. 19, 2003, the entire contents of which are hereby incorporated by reference into this application.

The present invention relates to a method of fabrication of semiconductor integrated circuit devices, and, more particularly, to a technique that is effective when applied to the testing of semiconductor integrated circuit devices, including semiconductor memories.

Various techniques have been proposed with respect to test burn-in systems which evaluate and determine the acceptability of semiconductor integrated circuit devices that constitute devices to be tested in burn-in. An example of such proposals is Japanese Unexamined Patent Publication No. Hei 06(1994)-283657 (Patent Document 1). As described in Patent Document 1, test burn-in systems are based on batch processing.

There are various test techniques for test burn-in systems. Examples include: Japanese Unexamined Patent Publication No. 2003-57292 (Patent Document 2), Japanese Unexamined Patent Publication No. 2000-40390 (Patent Document 3), and Japanese Unexamined Patent Publication No. Hei 05(1993)-55328 (Patent Document 4). Patent Document 2 discloses a technique wherein burn-in boards are divided into test groups and signals are supplied on a test group-by-test group basis in burn-in. Patent Document 3 discloses a technique wherein semiconductor integrated circuit devices are divided into a plurality of groups and semiconductor integrated circuit devices are subjected to pass/fail tests on a group-by-group basis. Patent Document 4 discloses a technique wherein, with voltage continuously applied, semiconductor integrated circuit devices are transported in a thermostatic bath and each semiconductor integrated circuit device is subjected to electrical tests at a test station. [Patent Document 1] Japanese Unexamined Patent Publication No. Hei 06(1994)-283657

[Patent Document 2] Japanese Unexamined Patent Publication No. 2003-57292

[Patent Document 3] Japanese Unexamined Patent Publication No. 2000-40390

[Patent Document 4] Japanese Unexamined Patent Publication No. Hei 05(1993)-55328

Semiconductor integrated circuit devices that are tested using test burn-in systems include a SiP (System in Package). This type of semiconductor integrated circuit device is a product obtained by stacking a plurality of semiconductor chips of logics, such as microcomputers, and semiconductor memories, and encapsulating them in a package.

The SiP is expected to significantly grow in demand in the future. To enhance the manufacturing efficiency, consideration has been given to shortening the time required for testing the semiconductor memory portion. The result of such consideration indicates that omission of burn-in and a shortening of the memory test time can be expected.

As a result, the test time has been significantly shortened. However, there still remains a problem even though the test time can be shortened. In batch processing, the throughput can be hardly enhanced because of the influence of the time required for attaching and detaching semiconductor integrated circuit devices and the setup.

By preparing a large number of test boards for testing semiconductor integrated circuit devices, the influence of the time required for attaching and detaching semiconductor integrated circuit devices and the setup can be reduced. However, a problem is left unsolved. The test boards are densely mounted with sockets into which semiconductor integrated circuit devices are inserted and peripheral circuits, including FPGAs (Field Programmable Gate Arrays), SRAMs (Static Random Access Memories), buffers, and the like. Preparing a large number of test boards can extraordinarily increase the test cost.

One of the possible methods for carrying out memory tests on SiPs, other than batch methods, is a method in which common memory testers and handlers are employed. This method is based on the assumption that the test time is no more than several minutes, and the number of pieces simultaneously measurable is 256 pieces or so at the maximum. This can degrade the efficiency.

An object of the present invention is to shorten the time required for testing semiconductor integrated circuit devices.

Another object of the present invention is to significantly reduce the cost of testing semiconductor integrated circuit devices.

A further object of the present invention is to provide a test method which takes only a moderately long time and is suitable for testing semiconductor integrated circuit devices.

A still further object of the present invention is to provide a test technique which makes it possible to carry out memory tests on semiconductor integrated circuit devices, including a semiconductor memory, at low cost with the efficiency.

These and other objects and novel features of the present invention will become apparent from the description provided in the present specification and the accompanying drawings.

The following is a brief description of the gist of representative aspects of the invention laid open in this application.

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