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Fabrication method of semiconductor integrated circuit deviceRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Contacting Multiple Semiconductive Regions (i.e., Interconnects)Fabrication method of semiconductor integrated circuit device description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070072408, Fabrication method of semiconductor integrated circuit device. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] The present invention relates to a technique on fabrication of a semiconductor integrated circuit device, particularly a technique effective for the formation of a copper interconnection, using Damascene process. [0002] In recent processes of fabricating a semiconductor integrated circuit device wherein circuits are made highly fine and integrated to a very high degree, element-isolating trenches are made in a silicon substrate or contact holes are made in self-alignment to gate elements of metal insulator semiconductor field effect transistors (MISFETs), for example, by using a difference in etching speed between different kinds of insulating films, such as a silicon oxide film and a silicon nitride film. [0003] Japanese Patent Unexamined Publication No. Hei 10(1998)-321838 discloses a technique of depositing a silicon oxide film across a silicon carbide (SiC) film over a gate electrode to which a side wall spacer made of a silicon oxide film or a silicon nitride film is fitted, thereby making contact holes in self-alignment to the gate electrode. For dry etching of the silicon oxide film, a hydrofluorocarbon gas or a fluorocarbon gas, such as CF.sub.4, CHF.sub.3 or C.sub.4F.sub.8, is used. When such a gas is used, the silicon carbide film, which is not easily etched, functions as an etching stopper for preventing the material of the gate electrode or the side wall spacer from being etched. In order to remove the silicon carbide film exposed to the bottom of the contact hole, plasma treatment using a mixed gas of CF.sub.4 and oxygen (O.sub.2) is utilized. When this plasma treatment is conducted, the silicon carbide film is converted to a silicon oxide film by the action of oxygen in the mixed gas and the film is removed by fluorine radicals and ions generated from CF.sub.4 in the mixed gas. [0004] Japanese Patent Unexamined Publication No. Hei 7(1995)-161690 discloses a technique in which at the time of supplying a mixed gas of a fluorine-based gas (for example, SF.sub.6, CF.sub.4 or NF.sub.3) and oxygen into a vacuum chamber wherein a silicon carbide substrate is arranged over an electrode and plasma is generated between the electrode and a counter electrode to etch the silicon carbide substrate with reactive ions, the substrate is arranged over the electrode in the state that the substrate is put on a plate which has a size approximated to the area of the electrode and is made of quartz glass or silicon. According to this method, the electrode, which has a larger area than the substrate, is covered with the plate; therefore, the material of the electrode (for example, aluminum) is prevented from being sputtered. Thus, it is possible to avoid a micromask phenomenon (a phenomenon that the electrode material is sputtered to adhere onto the surface of the substrate, thereby disturbing the advance of etching), which follows the sputtering. [0005] Japanese Patent Unexamined Publication No. 2000-355779 relates to an anticorrosion member of an etching machine, and discloses a technique in which the surface of a member exposed to an etching gas having an intense corrosiveness, such as chlorine-based or fluorine-based plasma gas, is covered with a silicon carbide film whose (1 1 1) plane is oriented in parallel to the member surface, the film being made of polycrystal of a 3C crystal system, in order to make anticorrosion of the member high. [0006] As a means for preventing etched-shape defects (such as a reversely-tapered shape and undercut) at the time of dry-etching a multilayered film wherein different kinds of films, such as a silicon oxide film, a silicon nitride film and an amorphous silicon film, are stacked, Japanese Patent Unexamined Publication No. Hei 6(1994)-208977 discloses a technique in which a mixed gas of CF.sub.4 and oxygen is used to dry-etch the multilayered film and subsequently SE gas or a mixed gas of SF.sub.6 and oxygen is used to dry-etch the multilayered film further in order to correct the defects of the etched shape. [0007] Japanese Patent Unexamined Publication No. Hei 7(1995)-235525 discloses a technique of introducing a fluorine-containing gas excited in a different space into a container of a dry etching machine containing a substrate to be treated from a first gas introducing port, and introducing a gas which contains a halogen element other than fluorine into the container from a second gas introducing port to perform etching, thereby etching a silicon nitride film over the substrate to be treated at a higher selective ratio (i.e., selectivity) than the selective ratio at which a silicon oxide film is etched. [0008] Japanese Patent Unexamined Publication No. Hei 5(1993)-326499 discloses a technique in which at the time of patterning a silicon nitride film used as an anti-oxidizing mask in LOCOS oxidization, an etching gas in which a gas for heightening an etching selective ratio of silicon nitride to resists and silicon oxide (for example, HBr or oxygen gas) is added to NF.sub.3 as a main etchant and is used to prevent side faces of the silicon nitride film from being forward-tapered, thereby suppressing bird's beak at end portions of field insulating films, which becomes a problem in LOCOS oxidization. [0009] Japanese Patent Unexamined Publication No. Hei 5(1993)-267246 discloses a technique in which at the time of patterning a silicon nitride film by reactive ion etching using a resist pattern as a mask, the following gas is used as an atmosphere gas for the etching to increase the etching selective ratio of the silicon nitride film to the resist: a first etching gas wherein SF.sub.6, HBr, He and oxygen are mixed, or a second etching gas wherein any one selected from nitrogen, flon gas, NF.sub.3 and inert gas is mixed with the first etching gas. [0010] Japanese Patent Unexamined Publication No. 2001-210627 discloses a technique of using an etching gas containing fluorine, carbon and nitrogen in order to plasma-etch satisfactorily an organic/inorganic hybrid film represented by SiCxHyOz and formed across an etching stopper film made of silicon carbide over interconnections made of aluminum or copper. SUMMARY OF THE INVENTION [0011] In recent years, interconnections have become very fine by a great rise in the integration degree of LSIs. Following this, an increase in interconnection resistance has become remarkable. Particularly in high-performance logic LSIs, the increase in interconnection resistance is a great factor of blocking a further improvement in the performance thereof. In order to solve this problem, the introduction of embedded Cu interconnections using the so-called Damascene process has been proposed, that is, a process of making interconnection grooves in an interlayer insulating film over a silicon substrate, depositing a Cu film on the interlayer insulating film including the inside space of the interconnection grooves, and removing the Cu film unnecessary outside the interconnection grooves by chemical mechanical polishing (CMP). Moreover, in order to promote a rise in the performance of logic LSIs by lowering the interconnection capacity thereof, the introduction of an interlayer insulating film made of an organic polymer-based insulating film material having a lower dielectric constant than a silicon oxide film has been advanced in parallel to the introduction of the above-mentioned Cu interconnections. [0012] In an ordinary process in which interconnection grooves are made in an interlayer insulating film made of the above-mentioned organic polymer-based insulating film material and then Cu interconnections are formed inside the grooves, a diffusion barrier layer is first deposited on the underlying Cu interconnections, and subsequently an interlayer insulating film is deposited on the diffusion barrier layer. The diffusion barrier layer is formed in order to prevent Cu in the underlying Cu interconnections from diffusing into the organic insulating film. The diffusion barrier layer is made of, for example, a silicon nitride film. In order to reduce interconnection capacity, it is desired to use silicon carbide having a smaller dielectric constant (=4.3 to 4.5) than a silicon nitride film (dielectric constant=7). [0013] Next, by dry-etching the organic insulating film and the diffusion barrier layer underlying it, interconnection grooves wherein the underlying Cu interconnections are exposed to its bottom are formed. Subsequently, a Cu film is deposited on the organic insulating film including the inside space of the interconnection grooves. Thereafter, the Cu film unnecessary on the organic insulating film is removed by chemical mechanical polishing, whereby Cu interconnections are formed inside the interconnection grooves. [0014] When the inventors dry-etched the silicon carbide film constituting the diffusion barrier layer, the inventors used a mixed gas of Ar, oxygen and a hydrofluorocarbon gas (or a fluorocarbon gas) such as CF.sub.4, CHF.sub.3 or C.sub.4F.sub.8. However, the following defects were generated: an insulating reactant adhered to the surface of the underlying Cu interconnections exposed to the bottom of the interconnection grooves and further the silicon carbide film or the organic insulating film exposed to side walls of the interconnection grooves was side-etched. [0015] An object of the present invention is to provide a technique making it possible to suppress the following defects: when an interlayer insulating film including a silicon carbide film and an organic insulating film is dry-etched to form interconnection grooves over underlying Cu interconnections, an insulating reactant adheres to the surface of the underlying Cu interconnections exposed to the bottom of the interconnection grooves and further the silicon carbide film or the organic insulating film exposed to side walls of the interconnection grooves is side-etched. [0016] The above-mentioned object of the present invention and other objects thereof, and new features thereof will be apparent from the description of the present specification and attached drawings. [0017] The summary of a typical aspect of the present invention will be briefly described as follows. [0018] (1) The process of fabricating a semiconductor integrated circuit device of the present invention comprises the steps of: [0019] (a) forming a conductive layer containing copper as a main component over a main face of a semiconductor substrate, [0020] (b) forming a first insulating film containing silicon carbide as a main component over the conductive layer, and [0021] (c) using a mixed gas of SF.sub.6 and NH.sub.3 to dry-etch a portion of the first insulating film, thereby making an opening wherein the surface of the conductive layer is exposed to its bottom. [0022] (2) The process of fabricating a semiconductor integrated circuit device of the present invention comprises the steps of: Continue reading about Fabrication method of semiconductor integrated circuit device... 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