| Extended instruction set for packet processing applications -> Monitor Keywords |
|
|
  Extended instruction set for packet processing applicationsUSPTO Application #: 20070074014Title: Extended instruction set for packet processing applications Abstract: A software program extension for a dynamic multi-streaming processor is disclosed. The extension comprising an instruction set enabling coordinated interaction between a packet management component and a core processing component of the processor. The software program comprises, a portion thereof for managing packet uploads and downloads into and out of memory, a portion thereof for managing specific memory allocations and de-allocations associated with enqueueing and dequeuing data packets, a portion thereof for managing the use of multiple contexts dedicated to the processing of a single data packet; and a portion thereof for managing selection and utilization of arithmetic and other context memory functions associated with data packet processing. The extension complements standard data packet processing program architecture for specific use for processors having a packet management unit that functions independently from a streaming processor unit. (end of abstract) Agent: Huffman Law Group, P.C. - Colorado Springs, CO, US Inventors: Enrique Musoll, Mario Nemirovsky, Stephen Melvin USPTO Applicaton #: 20070074014 - Class: 712300000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Byte-word Rearranging, Bit-field Insertion Or Extraction, String Length Detecting, Or Sequence Detecting The Patent Description & Claims data below is from USPTO Patent Application 20070074014. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED DOCUMENTS [0001] The present invention is a continuation in part (CIP) to a U.S. patent application Ser. No. 09/737,375 entitled "Queuing System for Processors in Packet Routing Operations" and filed on Dec. 14, 2000, which is included herein by reference. In addition, Ser. No. 09/737,375 claims priority benefit under 35 U.S.C. 119 (e) of Provisional Patent Application Ser. No. 60/181,364 filed on Feb. 8, 2000, and incorporates all disclosure of the prior applications by reference. FILED OF THE INVENTION [0002] The present invention is in the field of digital processing, pertains to apparatus and methods for processing packets in routers for packet networks, and more particularly to methods for providing packet management capability, especially in dynamic multi-streaming processors. BACKGROUND OF THE INVENTION [0003] The well-known Internet network is a notoriously well-known publicly-accessible communication network at the time of filing the present patent application, and arguably the most robust information and communication source ever made available. The Internet is used as a prime example in the present application of a data-packet-network which will benefit from the apparatus and methods taught in the present patent application, but is just one such network, following a particular standardized protocol. As is also very well known, the Internet (and related networks) are always a work in progress. That is, many researchers and developers are competing at all times to provide new and better apparatus and methods, including software, for enhancing the operation of such networks. [0004] In general the most sought-after improvements in data packet networks are those that provide higher speed in routing (more packets per unit time) and better reliability and fidelity in messaging. What is generally needed are router apparatus and methods increasing the rates at which packets may be processed in a router. [0005] As is well-known in the art, packet routers are computerized machines wherein data packets are received at any one or more of typically multiple ports, processed in some fashion, and sent out at the same or other ports of the router to continue on to downstream destinations. As an example of such computerized operations, keeping in mind that the Internet is a vast interconnected network of individual routers, individual routers have to keep track of which external routers to which they are connected by communication ports, and of which of alternate routes through the network are the best routes for incoming packets. Individual routers must also accomplish flow accounting, with a flow generally meaning a stream of packets with a common source and end destination. A general desire is that individual flows follow a common path. The skilled artisan will be aware of many such requirements for computerized processing. [0006] Typically a router in the Internet network will have one or more Central Processing Units (CPUs) as dedicated microprocessors for accomplishing the many computing tasks required. In the current art at the time of the present application, these are single-streaming processors; that is, each processor is capable of processing a single stream of instructions. In some cases developers are applying multiprocessor technology to such routing operations. The present inventors have been involved for some time in development of dynamic multistreaming (DMS) processors, which processors are capable of simultaneously processing multiple instruction streams. One preferred application for such processors is in the processing of packets in packet networks like the Internet. [0007] A dynamic multi-streaming (DMS) processor known to the inventor is capable of utilizing special hardware and a unique queuing system in order to alleviate the packet processing software of the system from certain packet management responsibilities, such as uploading into and downloading packets from memory. The special hardware is described with reference to Ser. No. 09/737,375 listed in the cross-reference section of this specification above. Using acronyms from the cross-referenced specification, the PMU is responsible for front-end packet management and the SPU is responsible for processing the packet information. [0008] Many prior art processors in the technology area of this patent application use MIPS (million instructions per second) architecture as a standard, and commands and instructions are necessarily MIPS-compatible. However, there are no prior art instruction sets that enable separated functions and coordination between an independently functioning PMU and the processing component described as an SPU. [0009] Also, there are no extended instructions for certain software operations made possible by a unique relationship between components of a DMS system as described in priority document Ser. No. 09/737,375. Therefore a goal of the present invention is to provided an extended set of instructions, which are compatible with the MIPS protocol and also can be used for special capabilities of a DMS processor engaged in the routing of data through a data packet network like the Internet network, for example. SUMMARY OF THE INVENTION [0010] In a preferred embodiment of the present invention, a software program extension for a dynamic multi-streaming processor is provided, the extension comprising an instruction set enabling coordinated interaction between a packet management component and a core processing component of the processor. The software program comprises, a portion thereof for managing packet uploads and downloads into and out of memory, a portion thereof for managing specific memory allocations and de-allocations associated with enqueueing and dequeuing data packets, a portion thereof for managing the use of multiple contexts dedicated to the processing of a single data packet; and a portion thereof for managing selection and utilization of arithmetic and other context memory functions associated with data packet processing. [0011] The extension, in preferred aspects, complements standard data packet processing program architecture for specific use for processors having a packet management unit that functions independently from a streaming processor unit. [0012] In a preferred embodiment, the dynamic multi-streaming processor functions as a data router coupled to a data packet network. In this preferred embodiment, the data packet network is the Internet network. In one aspect, the coordinated interaction includes communication of requests, commands, and notifications that do not require responses. In this aspect, the portion for managing packet uploads and downloads includes instructions for packet activation, packet completion, packet removal, packet identification, packet relocation, and packet update. [0013] Also in this aspect, the packet removal and packet relocation instructions are associated with removal of a packet from memory and relocating a packet from one portion of memory to another. In this aspect, the portion for managing memory allocations and de-allocations includes instructions for obtaining space in memory and for clearing previously allocated space in memory. [0014] In a preferred aspect, the memory is hardware controlled by a packet management component. In one aspect, the extension is supported by MIPS architecture. Also in preferred aspects, the portion for managing the use of multiple contexts includes instructions for obtaining an idle context, releasing an activated context, and for forcing nonuse of a context for predefined period of time. In the same preferred aspects, the portion for managing selection and utilization of arithmetic and other context memory functions includes instructions for gathering information from memory for loading into a context, distributing information from a context into memory, selecting and accessing at least one addition function, and for selecting and accessing at least one subtraction function. [0015] Now, for the first time, an extended set of instructions compatible with standard program architecture is provided for packet and memory management associated with a DMS processor engaged in the routing of data through a data packet network. BRIEF DESCRIPTION OF THE DRAWING FIGURES [0016] FIG. 1 is a simplified block diagram showing relationship of functional areas of a DMS processor in a preferred embodiment of the present invention. [0017] FIG. 2 is a block diagram of the DMS processor of FIG. 1 showing additional detail. [0018] FIG. 3 is a block diagram illustrating uploading of data into the LPM or EPM in an embodiment of the invention. [0019] FIG. 4a is a diagram illustrating determination and allocation for data uploading in an embodiment of the invention. Continue reading... Full patent description for Extended instruction set for packet processing applications Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Extended instruction set for packet processing applications patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Extended instruction set for packet processing applications or other areas of interest. ### Previous Patent Application: Dynamic retention of hardware register content in a computer system Next Patent Application: Control apparatus, upgrade method and program product of the same Industry Class: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) ### FreshPatents.com Support Thank you for viewing the Extended instruction set for packet processing applications patent info. IP-related news and info Results in 1.31081 seconds Other interesting Feshpatents.com categories: Qualcomm , Schering-Plough , Schlumberger , Seagate , Siemens , Texas Instruments , |
||
