| Exposure method -> Monitor Keywords |
|
|
 
Exposure methodExposure method description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070035716, Exposure method. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] The present invention relates generally to an exposure method, and more particularly to an optimization of an exposure condition. [0002] A conventional projection exposure apparatus uses a projection optical system to expose a reticle (or mask) pattern onto a plate, such as a single crystal substrate for a semiconductor wafer, and a glass plate for a liquid crystal display. In order to meet a demand for inexpensively supplying many electronic apparatuses, a method for manufacturing a device, such as a semiconductor chip (e.g., an LSI, a VLSI), a CCD, an LCD, a magnetic sensor, and a thin-film magnetic head), needs to improve the yield rate. This device manufacturing method includes various processes, such as exposure, development, and etching. In exposure, a conventional exposure apparatus considers not only the resolution at which the reticle pattern precisely resolve on a plate to be exposed, but also the influence on the other processes in the device manufacturing method. [0003] The optimizations of both the exposure condition and the reticle pattern are important for improved resolution. See, for example, Japanese Patent Applications, Publication Nos. 2005-26701 and 2002-319539. A reticle pattern is optimized, for example, through an optical proximity correction ("OPC"). A critical dimension ("CD") uniformity is known as a general conventional evaluation index of the resolution. See, for example, Japanese Patent Applications, Publication Nos. 2003-257819 and 2005-094015. Japanese Patent Application, Publication No. 9-319067 proposes a technology, called a process proximity control ("PPC"), which adds an etching error caused by the pattern density, to a reticle design in advance so as to correct the etching error. A simulation or a simulator may be used instead of actually exposing the plate for effective optimizations. [0004] Other prior art include, for example, SPIE 5379-15 Design rule optimization for 65-nm-node (CMOS5) BEOL using process and layout decomposition methodology and Evert Seevinck, Frans J. List, and Jan Lohstroh, "Static-Noise Margin Analysis of MOS SRAM Cells," IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October (1987). The above SPIE reference discloses a via chain as a test pattern under various design rules, measures the resistance, and determines whether the design rules and the OPC are properly set. [0005] As finer processing advances, an interaction between processes in the device manufacturing method becomes non-negligible, and the yield rate control over exposure only using the CD uniformity cannot necessarily improve the yield rate. Whether or not the device is defective as an electronic component depends upon the electrical characteristic of the device. A typical example of the electrical characteristic is a power supply voltage characteristic that is defined as a voltage change of the device to the power supply, but the electrical characteristic may be durability, resistance, electric capacity, etc. [0006] For a static RAM ("SRAM"), an illustrative electrical characteristic includes a static noise margin ("SNM") (see the above IEEE reference), V.sub.TH difference in a transistor gate, etc. The electrical characteristic to be verified differs according to device types. [0007] However, the evaluation index relating to the resolution does not always correspond to the electrical characteristic. For example, even when the CD uniformity is bad, the device is not defective in view of the electrical characteristic, and even when satisfying a predetermined CD uniformity, the device is defective in view of the electrical characteristic. BRIEF SUMMARY OF THE INVENTION [0008] The present invention is directed to an exposure method that can manufacture a device as a final product with a good yield rate. [0009] An exposure method according to one aspect of the present invention for exposing a pattern of a reticle onto a plate using a light from a light source and an optical system includes the steps of obtaining a relationship between an exposure parameter that determines a mode to expose a plate, and an electrical characteristic of a device derived from the device, determining whether the device obtained from the set exposure parameter has a predetermined electrical characteristic, and adjusting the set exposure parameter based on the relationship between the exposure parameter and the electrical characteristic, if said determining step determines that the device does not have the predetermined electrical characteristic. A database that stores a relationship used for the above exposure method, and a program for enabling a computer to implement the exposure method also constitute one aspect of the present invention. [0010] Other objects and further features of the present invention will become readily apparent from the following description of the preferred embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0011] FIG. 1 is a flowchart of an optimization algorithm according to the present invention. [0012] FIG. 2 is a flowchart for explaining a device manufacturing method according to the present invention. [0013] FIG. 3 is a flowchart of a step 4 shown in FIG. 2. [0014] FIG. 4 is a schematic block diagram of an exposure system that executes the optimization method shown in FIG. 1. [0015] FIG. 5 is a schematic block diagram as a variation of the exposure system shown in FIG. 4. [0016] FIG. 6 is a circuit diagram of an SRAM as one illustrative device manufactured in FIGS. 2 and 3. [0017] FIG. 7 is a graph for explaining a characteristic of static noise margin ("SNM") in the SRAM shown in FIG. 6. [0018] FIG. 8 is a circuit diagram of the SRAM shown in FIG. 6 that assumes a switching noise equivalent circuit. [0019] FIG. 9 is a graph for explaining a size of SNM when a cell ratio is changed. [0020] FIG. 10 shows a cell structure of the SRAM shown in FIG. 6. [0021] FIG. 11A to 11E are layer structures in the SRAM shown in FIG. 10. Continue reading about Exposure method... Full patent description for Exposure method Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Exposure method patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Exposure method or other areas of interest. ### Previous Patent Application: Lithographic apparatus and device manufacturing method utilizing a metrology system Next Patent Application: Contact lithography apparatus, system and method Industry Class: Photocopying ### FreshPatents.com Support Thank you for viewing the Exposure method patent info. IP-related news and info Results in 0.13762 seconds Other interesting Feshpatents.com categories: Tyco , Unilever , Warner-lambert , 3m 174 |
 * Protect your Inventions * US Patent Office filing 
PATENT INFO |
|
